3908253038
This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
71 lines
3.2 KiB
C
71 lines
3.2 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_MM_TSS_H_
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#define CPU_X86_MM_TSS_H_
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#include <stdint.h>
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/**
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* Task State Segment. Used by the CPU to manage switching between
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* different protection domains (tasks). The current task is referenced
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* by the Task Register. When the CPU switches away from a task due to
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* a far call, etc., it updates the associated in-memory TSS with the
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* current state of the task. It then loads CPU state from the TSS for
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* the new task. See Intel Combined Manual, Vol. 3, Chapter 7 for more
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* details.
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*/
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typedef struct tss {
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uint32_t prev_tsk; /**< The selector of the task that called this one, if applicable */
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uint32_t esp0; /**< Stack pointer for ring 0 code in this task */
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uint32_t ss0; /**< Stack segment selector for ring 0 code in this task */
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uint32_t esp1; /**< Stack pointer for ring 1 code in this task */
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uint32_t ss1; /**< Stack segment selector for ring 1 code in this task */
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uint32_t esp2; /**< Stack pointer for ring 2 code in this task */
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uint32_t ss2; /**< Stack segment selector for ring 2 code in this task */
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uint32_t cr3; /**< CR3 for this task when paging is enabled */
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uint32_t eip; /**< Stored instruction pointer value */
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uint32_t eflags; /**< Settings for EFLAGS register */
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/** General purpose register values */
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uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
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/** Segment register selector values */
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uint32_t es, cs, ss, ds, fs, gs;
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/** Selector for Local Descriptor Table */
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uint32_t ldt;
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/** Debug-related flag */
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uint16_t t;
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/** Offset from base of TSS to base of IO permission bitmap, if one is installed */
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uint16_t iomap_base;
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} tss_t;
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void tss_init(void);
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#endif /* CPU_X86_TSS_H_ */
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