c5ecde4ca0
- First in 8051def.h, it appears the uip_arch-asm.S file was copied from z80 and am unsure it will work properly. I modified the 8051def.h to prevent the UIP code from using these routines. - In dma.c the config routine provides access to all of the DMA channel options, except for the word mode flag. In order to maintain compatibility with any existing code I created a second routine and converted the original routine into a wrapper routine with a fixed word mode value. - uart.c::uart0_init was missing blocking access to the higher baud rates. I am not sure why, so I corrected this. - I also copied over to header files that provide some useful macros from the msp430 cpu. The files are lpm.h and hwconf.h. The lpm.h is for switching power modes, I think. The hwconf.h has various macros for configuring port I/O. By porting these files the led/button api's can be ported with minimal modifications.
260 lines
6.1 KiB
C
260 lines
6.1 KiB
C
/**
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* \file
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* DMA driver
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* \author
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* Original: Martti Huttunen <martti@sensinode.com>
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* Port: Zach Shelby <zach@sensinode.com>
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*/
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#include <stdio.h>
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#include "contiki.h"
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#include "dev/dma.h"
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#include "cc2430_sfr.h"
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dma_config_t dma_conf[4];
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struct process * dma_callback[4];
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/*---------------------------------------------------------------------------*/
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void
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dma_init(void)
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{
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uint16_t tmp_ptr;
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memset(dma_conf, 0, 4*sizeof(dma_config_t));
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for(tmp_ptr = 0; tmp_ptr < 4; tmp_ptr++) {
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dma_callback[tmp_ptr] = 0;
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}
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tmp_ptr = (uint16_t) &(dma_conf[0]);
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DMA1CFGH = tmp_ptr >> 8;
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DMA1CFGL = tmp_ptr;
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IEN1_DMAIE = 1; /*enable DMA interrupts*/
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}
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/*---------------------------------------------------------------------------*/
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#ifdef HAVE_DMA
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/**
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* Configure a DMA channel except word mode.
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*
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* \param channel channel ID;
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* \param src source address;
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* \param src_inc source increment mode;
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* \param dst dest address;
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* \param dst_inc dest increment mode;
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* \param length maximum length;
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* \param vlen_mode variable length mode;
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* \param t_mode DMA transfer mode;
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* \param trigger DMA trigger;
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* \param proc process that is upon interrupt;
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*
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* \return Handle to DMA channel
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* \return 0 invalid channel
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*/
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xDMAHandle
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dma_config(uint8_t channel, void *src, dma_inc_t src_inc, void *dst, dma_inc_t dst_inc,
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uint16_t length, dma_vlen_t vlen_mode, dma_type_t t_mode, dma_trigger_t trigger,
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struct process * proc)
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{
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return dma_config2(channel,src,src_inc, dst, dst_inc, length, 0, vlen_mode, t_mode, trigger, proc);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Configure a DMA channel.
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*
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* \param channel channel ID;
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* \param src source address;
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* \param src_inc source increment mode;
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* \param dst dest address;
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* \param dst_inc dest increment mode;
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* \param length maximum length;
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* \param word_mode set to 1 for 16-bits per transfer;
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* \param vlen_mode variable length mode;
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* \param t_mode DMA transfer mode;
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* \param trigger DMA trigger;
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* \param proc process that is upon interrupt;
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*
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* \return Handle to DMA channel
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* \return 0 invalid channel
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*/
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xDMAHandle
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dma_config2(uint8_t channel, void *src, dma_inc_t src_inc, void *dst, dma_inc_t dst_inc,
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uint16_t length, uint8_t word_mode, dma_vlen_t vlen_mode, dma_type_t t_mode, dma_trigger_t trigger,
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struct process * proc)
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{
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if((!channel) || (channel > 4)) {
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return 0;
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}
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DMAIRQ &= ~(1 << channel);
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channel--;
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dma_conf[channel].src_h = ((uint16_t) src) >> 8;
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dma_conf[channel].src_l = ((uint16_t) src);
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dma_conf[channel].dst_h = ((uint16_t) dst) >> 8;
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dma_conf[channel].dst_l = ((uint16_t) dst);
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dma_conf[channel].len_h = vlen_mode + (length >> 8);
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dma_conf[channel].len_l = length;
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dma_conf[channel].t_mode = ((word_mode&0x1)<<7) | (t_mode << 5) | trigger;
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dma_conf[channel].addr_mode = (src_inc << 6) + (dst_inc << 4) + 2; /*DMA has priority*/
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/*Callback is defined*/
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if(proc) {
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dma_conf[channel].addr_mode |= 8; /*set IRQMASK*/
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IEN1_DMAIE = 1; /*enable DMA interrupts*/
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}
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dma_callback[channel] = proc;
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return (xDMAHandle)channel + 1;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Arm a DMA channel.
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*
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* \param channel channel handle;
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*
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* \return pdTRUE
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* \return pdFALSE semaphore creation failed
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*/
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uint8_t
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dma_arm(xDMAHandle channel)
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{
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uint8_t ch_id = ((uint8_t)channel);
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if(!ch_id || (ch_id > 4)) {
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return 0;
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}
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DMAARM |= (1 << ch_id);
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return 1;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Stop a DMA channel.
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*
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* \param channel channel handle;
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*
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* \return pdTRUE
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* \return pdFALSE semaphore creation failed
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*/
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uint8_t
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dma_abort(xDMAHandle channel)
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{
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uint8_t ch_id = ((uint8_t) channel);
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if(!ch_id || (ch_id > 4)) {
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return 0;
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}
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DMAARM = 0x80 + (1 << ch_id); /*ABORT + channel bit*/
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return 1;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Trigger a DMA channel.
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*
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* \param channel channel handle;
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*
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* \return pdTRUE
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* \return pdFALSE semaphore creation failed
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*/
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uint8_t
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dma_trigger(xDMAHandle channel)
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{
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uint8_t ch_id = ((uint8_t) channel);
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if(!ch_id || (ch_id > 4)) {
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return 0;
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}
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DMAREQ |= (1 << ch_id);
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return 1;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Get DMA state.
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*
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* \param channel channel handle;
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*
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* \return pdTRUE active
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* \return pdFALSE not active
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*/
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uint8_t
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dma_state(xDMAHandle channel)
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{
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uint8_t ch_id = ((uint8_t)channel);
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if(!ch_id || (ch_id > 4)) {
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return 0;
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}
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if((DMAIRQ &(1 << ch_id)) == 0) {
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return 1;
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}
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return 0;
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}
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/*---------------------------------------------------------------------------*/
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void
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dma_config_print(xDMAHandle channel)
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{
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uint8_t ch_id = channel - 1;
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if(ch_id > 4) {
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return;
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}
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printf("DMA channel %d @ %x %x ", ch_id, (uint16_t) &(dma_conf[ch_id]) >> 8, (uint16_t) &(dma_conf[ch_id]) & 0xFF);
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{
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uint8_t i;
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uint8_t *ptr = (uint8_t *)&(dma_conf[ch_id]);
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for(i = 0; i< 8; i++) {
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if(i != 0) {
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printf(":%02x", *ptr++);
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}
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}
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printf("\n");
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}
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}
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#endif
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/*---------------------------------------------------------------------------*/
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#ifdef HAVE_RF_DMA
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extern void rf_dma_callback_isr(void);
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#endif
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#ifdef SPI_DMA_RX
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extern void spi_rx_dma_callback(void);
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#endif
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/*---------------------------------------------------------------------------*/
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/**
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* DMA interrupt service routine.
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*
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* if callback defined a poll is made to that process
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*/
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void
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dma_ISR(void) __interrupt (DMA_VECTOR)
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{
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#ifdef HAVE_DMA
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uint8_t i;
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#endif
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EA=0;
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#ifdef HAVE_RF_DMA
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if((DMAIRQ & 1) != 0) {
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DMAIRQ &= ~1;
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DMAARM=0x81;
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rf_dma_callback_isr();
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}
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#endif
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#ifdef SPI_DMA_RX
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if((DMAIRQ & 0x08) != 0) {
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DMAIRQ &= ~(1 << 3);
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spi_rx_dma_callback();
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}
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#endif
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#ifdef HAVE_DMA
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for(i = 0; i < 4; i++) {
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if((DMAIRQ & (1 << i + 1)) != 0) {
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DMAIRQ &= ~(1 << i+1);
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if(dma_callback[i] != 0) {
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process_poll(dma_callback[i]);
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}
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}
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}
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#endif
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IRCON_DMAIF = 0;
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EA = 1;
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}
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/*---------------------------------------------------------------------------*/
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