812 lines
27 KiB
C
812 lines
27 KiB
C
/* Copyright (c) 2009, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Additional fixes for AVR contributed by:
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*
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* Colin O'Flynn coflynn@newae.com
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* Eric Gnoske egnoske@gmail.com
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* Blake Leverett bleverett@gmail.com
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* Mike Vidales mavida404@gmail.com
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* Kevin Brown kbrown3@uccs.edu
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* Nate Bohlmann nate@elfwerks.com
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* David Kopf dak664@embarqmail.com
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* Ivan Delamer delamer@ieee.com
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of the copyright holders nor the names of
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*
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*/
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/**
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* \addtogroup wireless
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* @{
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*/
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/**
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* \defgroup hal RF230 hardware level drivers
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* @{
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*/
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/**
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* \file
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* This file contains low-level radio driver code.
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* This version is optimized for use with the "barebones" RF230bb driver,
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* which communicates directly with the contiki core MAC layer.
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* It is optimized for speed at the expense of generality.
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*/
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#include "contiki-conf.h"
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#if DEBUGFLOWSIZE
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extern uint8_t debugflowsize,debugflow[DEBUGFLOWSIZE];
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#define DEBUGFLOW(c) if (debugflowsize<(DEBUGFLOWSIZE-1)) debugflow[debugflowsize++]=c
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#else
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#define DEBUGFLOW(c)
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#endif
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/*============================ INCLUDE =======================================*/
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#include <stdlib.h>
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#include "hal.h"
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#if defined(__AVR_ATmega128RFA1__)
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#include "atmega128rfa1_registermap.h"
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#elif defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
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#include "atmega256rfr2_registermap.h"
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#else
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#include "at86rf230_registermap.h"
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#endif
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extern void get_last_rx_packet_timestamp(void);
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/*============================ VARIABLES =====================================*/
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volatile extern signed char rf230_last_rssi;
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/*============================ CALLBACKS =====================================*/
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/*============================ IMPLEMENTATION ================================*/
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#if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
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/* AVR1281 with internal RF231 radio */
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#include <avr/interrupt.h>
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#elif defined(__AVR__)
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/*
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* AVR with hardware SPI tranfers (TODO: move to hw spi hal for avr cpu)
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*/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#define HAL_SPI_TRANSFER_OPEN() { \
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HAL_ENTER_CRITICAL_REGION(); \
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HAL_SS_LOW(); /* Start the SPI transaction by pulling the Slave Select low. */
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#define HAL_SPI_TRANSFER_WRITE(to_write) (SPDR = (to_write))
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#define HAL_SPI_TRANSFER_WAIT() ({while ((SPSR & (1 << SPIF)) == 0) {;}}) /* gcc extension, alternative inline function */
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#define HAL_SPI_TRANSFER_READ() (SPDR)
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#define HAL_SPI_TRANSFER_CLOSE() \
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HAL_SS_HIGH(); /* End the transaction by pulling the Slave Select High. */ \
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HAL_LEAVE_CRITICAL_REGION(); \
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}
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#define HAL_SPI_TRANSFER(to_write) ( \
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HAL_SPI_TRANSFER_WRITE(to_write), \
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HAL_SPI_TRANSFER_WAIT(), \
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HAL_SPI_TRANSFER_READ() )
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#else /* __AVR__ */
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/*
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* Other SPI architecture (parts to core, parts to m16c6Xp
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*/
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#include "contiki-mulle.h" // MULLE_ENTER_CRITICAL_REGION
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// Software SPI transfers
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#define HAL_SPI_TRANSFER_OPEN() { uint8_t spiTemp; \
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HAL_ENTER_CRITICAL_REGION(); \
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HAL_SS_LOW(); /* Start the SPI transaction by pulling the Slave Select low. */
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#define HAL_SPI_TRANSFER_WRITE(to_write) (spiTemp = spiWrite(to_write))
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#define HAL_SPI_TRANSFER_WAIT() ({0;})
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#define HAL_SPI_TRANSFER_READ() (spiTemp)
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#define HAL_SPI_TRANSFER_CLOSE() \
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HAL_SS_HIGH(); /* End the transaction by pulling the Slave Select High. */ \
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HAL_LEAVE_CRITICAL_REGION(); \
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}
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#define HAL_SPI_TRANSFER(to_write) (spiTemp = spiWrite(to_write))
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inline uint8_t spiWrite(uint8_t byte)
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{
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uint8_t data = 0;
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uint8_t mask = 0x80;
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do
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{
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if( (byte & mask) != 0 )
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HAL_PORT_MOSI |= (1 << HAL_MOSI_PIN); //call MOSI.set();
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else
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HAL_PORT_MOSI &= ~(1 << HAL_MOSI_PIN); //call MOSI.clr();
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if( (HAL_PORT_MISO & (1 << HAL_MISO_PIN)) > 0) //call MISO.get() )
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data |= mask;
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HAL_PORT_SCK &= ~(1 << HAL_SCK_PIN); //call SCLK.clr();
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HAL_PORT_SCK |= (1 << HAL_SCK_PIN); //call SCLK.set();
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} while( (mask >>= 1) != 0 );
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return data;
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}
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#endif /* !__AVR__ */
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/** \brief This function initializes the Hardware Abstraction Layer.
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*/
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#if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
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void
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hal_init(void)
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{
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/*Reset variables used in file.*/
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/* (none at the moment) */
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}
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#elif defined(__AVR__)
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#define HAL_RF230_ISR() ISR(RADIO_VECT)
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void
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hal_init(void)
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{
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/*Reset variables used in file.*/
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/*IO Specific Initialization - sleep and reset pins. */
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/* Set pins low before they are initialized as output? Does not seem to matter */
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// hal_set_rst_low();
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// hal_set_slptr_low();
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DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */
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DDR_RST |= (1 << RST); /* Enable RST as output. */
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/*SPI Specific Initialization.*/
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/* Set SS, CLK and MOSI as output. */
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/* To avoid a SPI glitch, the port register shall be set before the DDR register */
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HAL_PORT_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK); /* Set SS and CLK high */
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HAL_DDR_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK) | (1 << HAL_DD_MOSI);
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HAL_DDR_SPI &=~ (1<< HAL_DD_MISO); /* MISO input */
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/* Run SPI at max speed */
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SPCR = (1 << SPE) | (1 << MSTR); /* Enable SPI module and master operation. */
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SPSR = (1 << SPI2X); /* Enable doubled SPI speed in master mode. */
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/* Enable interrupts from the radio transceiver. */
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hal_enable_trx_interrupt();
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}
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#else /* __AVR__ */
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#define HAL_RF230_ISR() M16C_INTERRUPT(M16C_INT1)
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#define HAL_TIME_ISR() M16C_INTERRUPT(M16C_TMRB4)
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#define HAL_TICK_UPCNT() (0xFFFF-TB4) // TB4 counts down so we need to convert it to upcounting
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void
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hal_init(void)
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{
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/*Reset variables used in file.*/
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/*IO Specific Initialization - sleep and reset pins. */
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DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */
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DDR_RST |= (1 << RST); /* Enable RST as output. */
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/*SPI Specific Initialization.*/
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/* Set SS, CLK and MOSI as output. */
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HAL_DDR_SS |= (1 << HAL_SS_PIN);
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HAL_DDR_SCK |= (1 << HAL_SCK_PIN);
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HAL_DDR_MOSI |= (1 << HAL_MOSI_PIN);
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HAL_DDR_MISO &= ~(1 << HAL_MISO_PIN);
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/* Set SS */
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HAL_PORT_SS |= (1 << HAL_SS_PIN); // HAL_SS_HIGH()
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HAL_PORT_SCK &= ~(1 << HAL_SCK_PIN); // SCLK.clr()
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/*TIMER Specific Initialization.*/
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// Init count source (Timer B3)
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TB3 = ((16*10) - 1); // 16 us ticks
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TB3MR.BYTE = 0b00000000; // Timer mode, F1
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TBSR.BIT.TB3S = 1; // Start Timer B3
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TB4 = 0xFFFF; //
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TB4MR.BYTE = 0b10000001; // Counter mode, count TB3
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TBSR.BIT.TB4S = 1; // Start Timer B4
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INT1IC.BIT.POL = 1; // Select rising edge
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HAL_ENABLE_OVERFLOW_INTERRUPT(); /* Enable Timer overflow interrupt. */
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/* Enable interrupts from the radio transceiver. */
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hal_enable_trx_interrupt();
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}
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#endif /* !__AVR__ */
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#if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
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/* Hack for internal radio registers. hal_register_read and hal_register_write are
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handled through defines, but the preprocesser can't parse a macro containing
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another #define with multiple arguments, e.g. using
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#define hal_subregister_read( address, mask, position ) (address&mask)>>position
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#define SR_TRX_STATUS TRX_STATUS, 0x1f, 0
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the following only sees 1 argument to the macro
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return hal_subregister_read(SR_TRX_STATUS);
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Possible fix is through two defines:
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#define x_hal_subregister_read(x) hal_subregister_read(x);
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#define hal_subregister_read( address, mask, position ) (address&mask)>>position
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but the subregister defines in atmega128rfa1_registermap.h are currently set up without
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the _SFR_MEM8 attribute, for use by hal_subregister_write.
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*/
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uint8_t
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hal_subregister_read(uint16_t address, uint8_t mask, uint8_t position)
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{
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return (_SFR_MEM8(address)&mask)>>position;
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}
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void
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hal_subregister_write(uint16_t address, uint8_t mask, uint8_t position,
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uint8_t value)
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{
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HAL_ENTER_CRITICAL_REGION();
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uint8_t register_value = _SFR_MEM8(address);
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register_value &= ~mask;
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value <<= position;
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value &= mask;
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value |= register_value;
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_SFR_MEM8(address) = value;
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HAL_LEAVE_CRITICAL_REGION();
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}
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#else /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
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/*----------------------------------------------------------------------------*/
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/** \brief This function reads data from one of the radio transceiver's registers.
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*
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* \param address Register address to read from. See datasheet for register
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* map.
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*
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* \see Look at the at86rf230_registermap.h file for register address definitions.
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*
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* \returns The actual value of the read register.
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*/
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uint8_t
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hal_register_read(uint8_t address)
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{
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uint8_t register_value;
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/* Add the register read command to the register address. */
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/* Address should be < 0x2f so no need to mask */
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// address &= 0x3f;
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address |= 0x80;
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HAL_SPI_TRANSFER_OPEN();
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/*Send Register address and read register content.*/
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HAL_SPI_TRANSFER(address);
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register_value = HAL_SPI_TRANSFER(0);
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HAL_SPI_TRANSFER_CLOSE();
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return register_value;
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}
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/*----------------------------------------------------------------------------*/
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/** \brief This function writes a new value to one of the radio transceiver's
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* registers.
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*
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* \see Look at the at86rf230_registermap.h file for register address definitions.
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*
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* \param address Address of register to write.
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* \param value Value to write.
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*/
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void
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hal_register_write(uint8_t address, uint8_t value)
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{
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/* Add the Register Write (short mode) command to the address. */
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address = 0xc0 | address;
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HAL_SPI_TRANSFER_OPEN();
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/*Send Register address and write register content.*/
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HAL_SPI_TRANSFER(address);
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HAL_SPI_TRANSFER(value);
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HAL_SPI_TRANSFER_CLOSE();
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}
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/*----------------------------------------------------------------------------*/
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/** \brief This function reads the value of a specific subregister.
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*
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* \see Look at the at86rf230_registermap.h file for register and subregister
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* definitions.
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*
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* \param address Main register's address.
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* \param mask Bit mask of the subregister.
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* \param position Bit position of the subregister
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* \retval Value of the read subregister.
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*/
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uint8_t
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hal_subregister_read(uint8_t address, uint8_t mask, uint8_t position)
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{
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/* Read current register value and mask out subregister. */
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uint8_t register_value = hal_register_read(address);
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register_value &= mask;
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register_value >>= position; /* Align subregister value. */
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return register_value;
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}
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/*----------------------------------------------------------------------------*/
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/** \brief This function writes a new value to one of the radio transceiver's
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* subregisters.
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*
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* \see Look at the at86rf230_registermap.h file for register and subregister
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* definitions.
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*
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* \param address Main register's address.
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* \param mask Bit mask of the subregister.
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* \param position Bit position of the subregister
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* \param value Value to write into the subregister.
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*/
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void
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hal_subregister_write(uint8_t address, uint8_t mask, uint8_t position,
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uint8_t value)
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{
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/* Read current register value and mask area outside the subregister. */
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volatile uint8_t register_value = hal_register_read(address);
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register_value &= ~mask;
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/* Start preparing the new subregister value. shift in place and mask. */
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value <<= position;
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value &= mask;
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value |= register_value; /* Set the new subregister value. */
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/* Write the modified register value. */
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hal_register_write(address, value);
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}
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#endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
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/*----------------------------------------------------------------------------*/
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/** \brief Transfer a frame from the radio transceiver to a RAM buffer
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*
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* This version is optimized for use with contiki RF230BB driver.
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* The callback routine and CRC are left out for speed in reading the rx buffer.
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* Any delays here can lead to overwrites by the next packet!
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*
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* If the frame length is out of the defined bounds, the length, lqi and crc
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* are set to zero.
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*
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* \param rx_frame Pointer to the data structure where the frame is stored.
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*/
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void
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hal_frame_read(hal_rx_frame_t *rx_frame)
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{
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#if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
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uint8_t frame_length,*rx_data,*rx_buffer;
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/* Get length from the TXT_RX_LENGTH register, not including LQI
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* Bypassing the length check can result in overrun if buffer is < 256 bytes.
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*/
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frame_length = TST_RX_LENGTH;
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if ((frame_length < HAL_MIN_FRAME_LENGTH) || (frame_length > HAL_MAX_FRAME_LENGTH)) {
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/* Length test failed */
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rx_frame->length = 0;
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rx_frame->lqi = 0;
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rx_frame->crc = false;
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return;
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}
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rx_frame->length = frame_length;
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/* Start of buffer in I/O space, pointer to RAM buffer */
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rx_buffer=(uint8_t *)0x180;
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rx_data = (rx_frame->data);
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do{
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*rx_data++ = _SFR_MEM8(rx_buffer++);
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} while (--frame_length > 0);
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/*Read LQI value for this frame.*/
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rx_frame->lqi = *rx_buffer;
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/* If crc was calculated set crc field in hal_rx_frame_t accordingly.
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* Else show the crc has passed the hardware check.
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*/
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rx_frame->crc = true;
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#else /* */
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uint8_t frame_length, *rx_data;
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/*Send frame read (long mode) command.*/
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HAL_SPI_TRANSFER_OPEN();
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HAL_SPI_TRANSFER(0x20);
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/*Read frame length. This includes the checksum. */
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frame_length = HAL_SPI_TRANSFER(0);
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/*Check for correct frame length. Bypassing this test can result in a buffer overrun! */
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if ((frame_length < HAL_MIN_FRAME_LENGTH) || (frame_length > HAL_MAX_FRAME_LENGTH)) {
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/* Length test failed */
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rx_frame->length = 0;
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rx_frame->lqi = 0;
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rx_frame->crc = false;
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}
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else {
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rx_data = (rx_frame->data);
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rx_frame->length = frame_length;
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/*Transfer frame buffer to RAM buffer */
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HAL_SPI_TRANSFER_WRITE(0);
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HAL_SPI_TRANSFER_WAIT();
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do{
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*rx_data++ = HAL_SPI_TRANSFER_READ();
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HAL_SPI_TRANSFER_WRITE(0);
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/* CRC was checked in hardware, but redoing the checksum here ensures the rx buffer
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* is not being overwritten by the next packet. Since that lengthy computation makes
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* such overwrites more likely, we skip it and hope for the best.
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* Without the check a full buffer is read in 320us at 2x spi clocking.
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* The 802.15.4 standard requires 640us after a greater than 18 byte frame.
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* With a low interrupt latency overwrites should never occur.
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*/
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// crc = _crc_ccitt_update(crc, tempData);
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HAL_SPI_TRANSFER_WAIT();
|
|
|
|
} while (--frame_length > 0);
|
|
|
|
|
|
/*Read LQI value for this frame.*/
|
|
rx_frame->lqi = HAL_SPI_TRANSFER_READ();
|
|
|
|
/* If crc was calculated set crc field in hal_rx_frame_t accordingly.
|
|
* Else show the crc has passed the hardware check.
|
|
*/
|
|
rx_frame->crc = true;
|
|
}
|
|
|
|
HAL_SPI_TRANSFER_CLOSE();
|
|
|
|
#endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/** \brief This function will download a frame to the radio transceiver's frame
|
|
* buffer.
|
|
*
|
|
* \param write_buffer Pointer to data that is to be written to frame buffer.
|
|
* \param length Length of data. The maximum length is 127 bytes.
|
|
*/
|
|
void
|
|
hal_frame_write(uint8_t *write_buffer, uint8_t length)
|
|
{
|
|
#if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
|
|
uint8_t *tx_buffer;
|
|
tx_buffer=(uint8_t *)0x180; //start of fifo in i/o space
|
|
/* Write frame length, including the two byte checksum */
|
|
/* The top bit of the length field shall be set to 0 for IEEE 802.15.4 compliant frames */
|
|
/* It should already be clear, so bypassing the masking is sanity check of the uip stack */
|
|
// length &= 0x7f;
|
|
_SFR_MEM8(tx_buffer++) = length;
|
|
|
|
/* Download to the Frame Buffer.
|
|
* When the FCS is autogenerated there is no need to transfer the last two bytes
|
|
* since they will be overwritten.
|
|
*/
|
|
#if !RF230_CONF_CHECKSUM
|
|
length -= 2;
|
|
#endif
|
|
do _SFR_MEM8(tx_buffer++)= *write_buffer++; while (--length);
|
|
|
|
#else /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
|
|
/* Optionally truncate length to maximum frame length.
|
|
* Not doing this is a fast way to know when the application needs fixing!
|
|
*/
|
|
// length &= 0x7f;
|
|
|
|
HAL_SPI_TRANSFER_OPEN();
|
|
|
|
/* Send Frame Transmit (long mode) command and frame length */
|
|
HAL_SPI_TRANSFER(0x60);
|
|
HAL_SPI_TRANSFER(length);
|
|
|
|
/* Download to the Frame Buffer.
|
|
* When the FCS is autogenerated there is no need to transfer the last two bytes
|
|
* since they will be overwritten.
|
|
*/
|
|
#if !RF230_CONF_CHECKSUM
|
|
length -= 2;
|
|
#endif
|
|
do HAL_SPI_TRANSFER(*write_buffer++); while (--length);
|
|
|
|
HAL_SPI_TRANSFER_CLOSE();
|
|
#endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
#if 0 //Uses 80 bytes (on Raven) omit unless needed
|
|
/** \brief Read SRAM
|
|
*
|
|
* This function reads from the SRAM of the radio transceiver.
|
|
*
|
|
* \param address Address in the TRX's SRAM where the read burst should start
|
|
* \param length Length of the read burst
|
|
* \param data Pointer to buffer where data is stored.
|
|
*/
|
|
void
|
|
hal_sram_read(uint8_t address, uint8_t length, uint8_t *data)
|
|
{
|
|
HAL_SPI_TRANSFER_OPEN();
|
|
|
|
/*Send SRAM read command and address to start*/
|
|
HAL_SPI_TRANSFER(0x00);
|
|
HAL_SPI_TRANSFER(address);
|
|
|
|
HAL_SPI_TRANSFER_WRITE(0);
|
|
HAL_SPI_TRANSFER_WAIT();
|
|
|
|
/*Upload the chosen memory area.*/
|
|
do{
|
|
*data++ = HAL_SPI_TRANSFER_READ();
|
|
HAL_SPI_TRANSFER_WRITE(0);
|
|
HAL_SPI_TRANSFER_WAIT();
|
|
} while (--length > 0);
|
|
|
|
HAL_SPI_TRANSFER_CLOSE();
|
|
}
|
|
#endif
|
|
/*----------------------------------------------------------------------------*/
|
|
#if 0 //omit unless needed
|
|
/** \brief Write SRAM
|
|
*
|
|
* This function writes into the SRAM of the radio transceiver. It can reduce
|
|
* SPI transfers if only part of a frame is to be changed before retransmission.
|
|
*
|
|
* \param address Address in the TRX's SRAM where the write burst should start
|
|
* \param length Length of the write burst
|
|
* \param data Pointer to an array of bytes that should be written
|
|
*/
|
|
void
|
|
hal_sram_write(uint8_t address, uint8_t length, uint8_t *data)
|
|
{
|
|
HAL_SPI_TRANSFER_OPEN();
|
|
|
|
/*Send SRAM write command.*/
|
|
HAL_SPI_TRANSFER(0x40);
|
|
|
|
/*Send address where to start writing to.*/
|
|
HAL_SPI_TRANSFER(address);
|
|
|
|
/*Upload the chosen memory area.*/
|
|
do{
|
|
HAL_SPI_TRANSFER(*data++);
|
|
} while (--length > 0);
|
|
|
|
HAL_SPI_TRANSFER_CLOSE();
|
|
|
|
}
|
|
#endif
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* This #if compile switch is used to provide a "standard" function body for the */
|
|
/* doxygen documentation. */
|
|
#if defined(DOXYGEN)
|
|
/** \brief ISR for the radio IRQ line, triggered by the input capture.
|
|
* This is the interrupt service routine for timer1.ICIE1 input capture.
|
|
* It is triggered of a rising edge on the radio transceivers IRQ line.
|
|
*/
|
|
void RADIO_VECT(void);
|
|
#else /* !DOXYGEN */
|
|
/* These link to the RF230BB driver in rf230.c */
|
|
void rf230_interrupt(void);
|
|
|
|
extern hal_rx_frame_t rxframe[RF230_CONF_RX_BUFFERS];
|
|
extern uint8_t rxframe_head,rxframe_tail;
|
|
|
|
/* rf230interruptflag can be printed in the main idle loop for debugging */
|
|
#define DEBUG 0
|
|
#if DEBUG
|
|
volatile char rf230interruptflag;
|
|
#define INTERRUPTDEBUG(arg) rf230interruptflag=arg
|
|
#else
|
|
#define INTERRUPTDEBUG(arg)
|
|
#endif
|
|
|
|
#if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
|
|
/* The atmega128rfa1 has individual interrupts for the integrated radio'
|
|
* Whichever are enabled by the RF230 driver must be present even if not used!
|
|
*/
|
|
/* Received packet interrupt */
|
|
ISR(TRX24_RX_END_vect)
|
|
{
|
|
/* Get the rssi from ED if extended mode */
|
|
#if RF230_CONF_AUTOACK
|
|
rf230_last_rssi=hal_register_read(RG_PHY_ED_LEVEL);
|
|
#endif
|
|
|
|
/* Buffer the frame and call rf230_interrupt to schedule poll for rf230 receive process */
|
|
/* Is a ram buffer available? */
|
|
if (rxframe[rxframe_tail].length) {DEBUGFLOW('0');} else /*DEBUGFLOW('1')*/;
|
|
|
|
#ifdef RF230_MIN_RX_POWER
|
|
/* Discard packets weaker than the minimum if defined. This is for testing miniature meshes */
|
|
/* This does not prevent an autoack. TODO:rfa1 radio can be set up to not autoack weak packets */
|
|
if (rf230_last_rssi >= RF230_MIN_RX_POWER) {
|
|
#else
|
|
if (1) {
|
|
#endif
|
|
// DEBUGFLOW('2');
|
|
hal_frame_read(&rxframe[rxframe_tail]);
|
|
rxframe_tail++;if (rxframe_tail >= RF230_CONF_RX_BUFFERS) rxframe_tail=0;
|
|
rf230_interrupt();
|
|
}
|
|
}
|
|
/* Preamble detected, starting frame reception */
|
|
ISR(TRX24_RX_START_vect)
|
|
{
|
|
// DEBUGFLOW('3');
|
|
/* Save RSSI for this packet if not in extended mode, scaling to 1dB resolution */
|
|
#if !RF230_CONF_AUTOACK
|
|
rf230_last_rssi = 3 * hal_subregister_read(SR_RSSI);
|
|
#endif
|
|
get_last_rx_packet_timestamp();
|
|
}
|
|
|
|
/* PLL has locked, either from a transition out of TRX_OFF or a channel change while on */
|
|
ISR(TRX24_PLL_LOCK_vect)
|
|
{
|
|
// DEBUGFLOW('4');
|
|
}
|
|
|
|
/* PLL has unexpectedly unlocked */
|
|
ISR(TRX24_PLL_UNLOCK_vect)
|
|
{
|
|
DEBUGFLOW('5');
|
|
}
|
|
/* Flag is set by the following interrupts */
|
|
extern volatile uint8_t rf230_wakewait, rf230_txendwait,rf230_ccawait;
|
|
|
|
/* Wake has finished */
|
|
ISR(TRX24_AWAKE_vect)
|
|
{
|
|
// DEBUGFLOW('6');
|
|
rf230_wakewait=0;
|
|
}
|
|
|
|
/* Transmission has ended */
|
|
ISR(TRX24_TX_END_vect)
|
|
{
|
|
// DEBUGFLOW('7');
|
|
rf230_txendwait=0;
|
|
}
|
|
|
|
/* Frame address has matched ours */
|
|
ISR(TRX24_XAH_AMI_vect)
|
|
{
|
|
// DEBUGFLOW('8');
|
|
}
|
|
|
|
/* CCAED measurement has completed */
|
|
ISR(TRX24_CCA_ED_DONE_vect)
|
|
{
|
|
DEBUGFLOW('4');
|
|
rf230_ccawait=0;
|
|
}
|
|
|
|
#else /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
|
|
/* Separate RF230 has a single radio interrupt and the source must be read from the IRQ_STATUS register */
|
|
HAL_RF230_ISR()
|
|
{
|
|
volatile uint8_t state;
|
|
uint8_t interrupt_source; /* used after HAL_SPI_TRANSFER_OPEN/CLOSE block */
|
|
|
|
INTERRUPTDEBUG(1);
|
|
|
|
|
|
/* Using SPI bus from ISR is generally a bad idea... */
|
|
/* Note: all IRQ are not always automatically disabled when running in ISR */
|
|
HAL_SPI_TRANSFER_OPEN();
|
|
|
|
/*Read Interrupt source.*/
|
|
/*Send Register address and read register content.*/
|
|
HAL_SPI_TRANSFER_WRITE(0x80 | RG_IRQ_STATUS);
|
|
|
|
HAL_SPI_TRANSFER_WAIT(); /* AFTER possible interleaved processing */
|
|
|
|
interrupt_source = HAL_SPI_TRANSFER(0);
|
|
|
|
HAL_SPI_TRANSFER_CLOSE();
|
|
|
|
/*Handle the incomming interrupt. Prioritized.*/
|
|
if ((interrupt_source & HAL_RX_START_MASK)){
|
|
INTERRUPTDEBUG(10);
|
|
/* Save RSSI for this packet if not in extended mode, scaling to 1dB resolution */
|
|
#if !RF230_CONF_AUTOACK
|
|
#if 0 // 3-clock shift and add is faster on machines with no hardware multiply
|
|
// With -Os avr-gcc saves a byte by using the general routine for multiply by 3
|
|
rf230_last_rssi = hal_subregister_read(SR_RSSI);
|
|
rf230_last_rssi = (rf230_last_rssi <<1) + rf230_last_rssi;
|
|
#else // Faster with 1-clock multiply. Raven and Jackdaw have 2-clock multiply so same speed while saving 2 bytes of program memory
|
|
rf230_last_rssi = 3 * hal_subregister_read(SR_RSSI);
|
|
#endif
|
|
#endif
|
|
|
|
}
|
|
if (interrupt_source & HAL_TRX_END_MASK){
|
|
INTERRUPTDEBUG(11);
|
|
|
|
state = hal_subregister_read(SR_TRX_STATUS);
|
|
if((state == BUSY_RX_AACK) || (state == RX_ON) || (state == BUSY_RX) || (state == RX_AACK_ON)){
|
|
/* Received packet interrupt */
|
|
/* Buffer the frame and call rf230_interrupt to schedule poll for rf230 receive process */
|
|
if (rxframe[rxframe_tail].length) INTERRUPTDEBUG(42); else INTERRUPTDEBUG(12);
|
|
|
|
#ifdef RF230_MIN_RX_POWER
|
|
/* Discard packets weaker than the minimum if defined. This is for testing miniature meshes.*/
|
|
/* Save the rssi for printing in the main loop */
|
|
#if RF230_CONF_AUTOACK
|
|
//rf230_last_rssi=hal_subregister_read(SR_ED_LEVEL);
|
|
rf230_last_rssi=hal_register_read(RG_PHY_ED_LEVEL);
|
|
#endif
|
|
if (rf230_last_rssi >= RF230_MIN_RX_POWER) {
|
|
#endif
|
|
hal_frame_read(&rxframe[rxframe_tail]);
|
|
rxframe_tail++;if (rxframe_tail >= RF230_CONF_RX_BUFFERS) rxframe_tail=0;
|
|
rf230_interrupt();
|
|
#ifdef RF230_MIN_RX_POWER
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
if (interrupt_source & HAL_TRX_UR_MASK){
|
|
INTERRUPTDEBUG(13);
|
|
;
|
|
}
|
|
if (interrupt_source & HAL_PLL_UNLOCK_MASK){
|
|
INTERRUPTDEBUG(14);
|
|
;
|
|
}
|
|
if (interrupt_source & HAL_PLL_LOCK_MASK){
|
|
INTERRUPTDEBUG(15);
|
|
;
|
|
}
|
|
if (interrupt_source & HAL_BAT_LOW_MASK){
|
|
/* Disable BAT_LOW interrupt to prevent endless interrupts. The interrupt */
|
|
/* will continously be asserted while the supply voltage is less than the */
|
|
/* user-defined voltage threshold. */
|
|
uint8_t trx_isr_mask = hal_register_read(RG_IRQ_MASK);
|
|
trx_isr_mask &= ~HAL_BAT_LOW_MASK;
|
|
hal_register_write(RG_IRQ_MASK, trx_isr_mask);
|
|
INTERRUPTDEBUG(16);
|
|
;
|
|
}
|
|
}
|
|
#endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
|
|
# endif /* defined(DOXYGEN) */
|
|
|
|
/** @} */
|
|
/** @} */
|
|
|
|
/*EOF*/
|