23e8090257
All drivers implemented so far are for chips which are only available on legacy x86 PCs. This commit moves them into a more appropriate folder, also making the cpu/x86/drivers/ folder ready for other x86 based SoCs.
86 lines
3.1 KiB
C
86 lines
3.1 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef PIC_H
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#define PIC_H
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#include "helpers.h"
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#define PIC1_CMD_PORT 0x20
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#define PIC1_DATA_PORT 0x21
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#define PIC2_CMD_PORT 0xA0
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#define PIC2_DATA_PORT 0xA1
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#define PIC1_OFFSET 0x20
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#define PIC2_OFFSET PIC1_OFFSET + 8
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/*
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* Returns the actual interrupt number of a given IRQ,
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* no matter which PIC it is part of.
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*/
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#define PIC_INT(a) (a + PIC1_OFFSET)
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void pic_unmask_irq(unsigned int num);
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/* This function initializes the daisy-chained Master and Slave 8259 PICs.
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* It is only called once, so let's give the compiler the option to inline it.
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* For more information about the ICWs, please refer to http://stanislavs.org/helppc/8259.html.
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*/
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static inline void
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pic_init(void)
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{
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/* ICW1: Initialization. */
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outb(PIC1_CMD_PORT, 0x11);
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outb(PIC2_CMD_PORT, 0x11);
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/* ICW2: Remap IRQs by setting an IDT Offset for each PIC. */
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outb(PIC1_DATA_PORT, PIC1_OFFSET);
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outb(PIC2_DATA_PORT, PIC2_OFFSET);
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/* ICW3: Setup Slave to Master's IRQ2. */
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outb(PIC1_DATA_PORT, 0x04);
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outb(PIC2_DATA_PORT, 0x02);
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/* ICW4: Environment setup. Set PIC1 as master and PIC2 as slave. */
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outb(PIC1_DATA_PORT, 0x01);
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outb(PIC2_DATA_PORT, 0x01);
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/* Set the IMR register, masking all hardware interrupts but IRQ 2.
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* We will have to unmask each IRQ when registering them. */
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outb(PIC1_DATA_PORT, 0xfb);
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outb(PIC2_DATA_PORT, 0xff);
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}
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/*
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* This function sends an end-of-interrupt (EOI) to the correct PIC according
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* to the IRQ line number.
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*/
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void pic_eoi(unsigned int irq);
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#endif /* PIC_H */
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