365 lines
12 KiB
C
365 lines
12 KiB
C
/** @file hal/micro/cortexm3/flash.c
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* @brief Implements the generic flash manipulation routines.
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*
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* The file 'flash-sw-spec.txt' should provide *all* the information needed
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* to understand and work with the FLITF and flash.
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*
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*
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* <!--(C) COPYRIGHT 2010 STMicroelectronics. All rights reserved. -->
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*/
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#include PLATFORM_HEADER
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#include "error.h"
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#include "hal/micro/cortexm3/bootloader/fib-bootloader.h"
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#include "hal/micro/cortexm3/mpu.h"
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#include "memmap.h"
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#include "flash.h"
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#ifdef FLASH_PROGRAMMING_WITH_EMPTY_FIB
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#define ST_EMU_TEST
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#endif
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// A translation table used to convert FibStatus codes to corresponding
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// StStatus values
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static const StStatus fibToStStatus[] = {
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ST_SUCCESS, // FIB_SUCCESS 0
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ST_BAD_ARGUMENT, // FIB_ERR_UNALIGNED 1
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ST_BAD_ARGUMENT, // FIB_ERR_INVALID_ADDRESS 2
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ST_BAD_ARGUMENT, // FIB_ERR_INVALID_TYPE 3
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ST_ERR_FLASH_PROG_FAIL, // FIB_ERR_WRITE_PROTECTED 4
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ST_ERR_FLASH_PROG_FAIL, // FIB_ERR_WRITE_FAILED 5
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ST_ERR_FLASH_WRITE_INHIBITED, // FIB_ERR_ERASE_REQUIRED 6
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ST_ERR_FLASH_VERIFY_FAILED // FIB_ERR_VERIFY_FAILED 7
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};
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//The purpose of flashEraseIsActive and halFlashEraseIsActive() is so that
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//interrupts can query the flash library to find out of Flash Erase is
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//active when their ISR gets invoked. This is useful because Flash Erase
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//causes the chip to go ATOMIC for 21ms and this delay will disrupt interrupt
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//latency. By having a sinple API that an ISR can query for this state,
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//the ISR can appriopriately adjust for a 21ms latency time.
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boolean flashEraseIsActive = FALSE;
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boolean halFlashEraseIsActive(void)
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{
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return flashEraseIsActive;
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}
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// Emulators do not have FIB bootloaders, so need to include a copy of
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// these core flash routines.
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#if defined(ST_EMU_TEST)
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static void enableFlitf(void)
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{
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//First, unlock the FLITF by writing the two key values to the Flash
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//Protection Unlock register
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FPEC_KEY = FPEC_KEY1;
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FPEC_KEY = FPEC_KEY2;
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//Second, unlock the CIB by writing the two key values to the CIB
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//Protection Unlock register
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OPT_KEY = FPEC_KEY1;
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OPT_KEY = FPEC_KEY2;
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//Turn on the FPEC clock for flash manipulation operations
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FPEC_CLKREQ = FPEC_CLKREQ_FIELD;
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//make sure the FPEC clock is running before we proceed
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while( (FPEC_CLKSTAT&FPEC_CLKACK) != FPEC_CLKACK) {}
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//just in case, wait until the flash is no longer busy
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while( (FLASH_STATUS&FLASH_STATUS_FLA_BSY) == FLASH_STATUS_FLA_BSY ) {}
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}
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static void disableFlitf(void)
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{
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//make sure the FPEC is completely idle before turning off the clock
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while( (FPEC_CLKSTAT&FPEC_CLKBSY) == FPEC_CLKBSY) {}
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//Turn off the FPEC clock now that we're done
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FPEC_CLKREQ = FPEC_CLKREQ_RESET;
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//Set LOCK and clear OPTWREN to lock both the FLITF and the CIB.
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//NOTE: The PROG bit must also be cleared otherwise Flash can still
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// be programmed even with the LOCK bit set. BugzID: 6267
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FLASH_CTRL = FLASH_CTRL_LOCK; //lock the flash from further accesses
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}
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static FibStatus fibFlashWrite(int32u address, int8u *data, int32u length, int32u dummy)
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{
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int32u i;
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int16u *ptr;
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FibStatus status = FIB_SUCCESS;
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// Address and length must be half-word aligned.
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if ((address & 1) || (length & 1)) {
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return FIB_ERR_UNALIGNED;
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}
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// Start and end address must be in MFB or CIB.
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if (!((address >= MFB_BOTTOM && address + length <= MFB_TOP + 1)
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|| (address >= CIB_BOTTOM && address + length <= CIB_TOP + 1))) {
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return FIB_ERR_INVALID_ADDRESS;
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}
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enableFlitf();
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ptr = (int16u *)address;
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for (i = 0; i < length; i += 2) {
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int16u currentData = *ptr;
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int16u newData = HIGH_LOW_TO_INT(data[i + 1], data[i]);
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// Only program the data if it makes sense to do so.
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if (currentData == newData) {
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// If the new data matches the flash, don't bother doing anything.
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} else if (currentData == 0xFFFF || newData == 0x0000) {
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// If the flash is 0xFFFF we're allowed to write anything.
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// If the new data is 0x0000 it doesn't matter what the flash is.
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// OPTWREN must stay set to keep CIB unlocked.
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if ((CIB_OB_BOTTOM <= (int32u)ptr) && ((int32u)ptr <= CIB_OB_TOP)) {
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FLASH_CTRL = (FLASH_CTRL_OPTWREN | FLASH_CTRL_OPTPROG);
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} else {
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FLASH_CTRL = (FLASH_CTRL_OPTWREN | FLASH_CTRL_PROG);
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}
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// Assigning data to the address performs the actual write.
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(*ptr) = newData;
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// Wait for the busy bit to clear, indicating operation is done.
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while ((FLASH_STATUS & FLASH_STATUS_FLA_BSY) != 0) {}
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// Reset the operation complete flag.
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FLASH_STATUS = FLASH_STATUS_EOP;
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// Check if any error bits have been tripped, and if so, exit.
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// The bit PAGE_PROG_ERR is not relevant in this programming mode.
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if (FLASH_STATUS & (FLASH_STATUS_WRP_ERR | FLASH_STATUS_PROG_ERR)) {
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if (FLASH_STATUS & FLASH_STATUS_WRP_ERR) {
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status = FIB_ERR_WRITE_PROTECTED;
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} else {
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status = FIB_ERR_WRITE_FAILED;
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}
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FLASH_STATUS = FLASH_STATUS_WRP_ERR;
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FLASH_STATUS = FLASH_STATUS_PROG_ERR;
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break;
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}
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} else {
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status = FIB_ERR_ERASE_REQUIRED;
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break;
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}
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ptr++;
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}
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disableFlitf();
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return status;
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}
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static FibStatus fibFlashWriteVerify(int32u address, int8u *data, int32u length)
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{
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int32u i;
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int8u *ptr = (int8u *)address;
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for (i = 0; i < length; i++) {
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if (*ptr != data[i]) {
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return FIB_ERR_VERIFY_FAILED;
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}
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ptr++;
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}
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return FIB_SUCCESS;
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}
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static FibStatus fibFlashErase(FibEraseType eraseType, int32u address)
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{
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int32u eraseOp;
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int32u *ptr;
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int32u length;
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FibStatus status = FIB_SUCCESS;
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if (BYTE_0(eraseType) == MFB_MASS_ERASE) {
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eraseOp = FLASH_CTRL_MASSERASE;
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ptr = (int32u *)MFB_BOTTOM;
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length = MFB_SIZE_W;
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} else if (BYTE_0(eraseType) == MFB_PAGE_ERASE) {
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if (address < MFB_BOTTOM || address > MFB_TOP) {
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return FIB_ERR_INVALID_ADDRESS;
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}
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eraseOp = FLASH_CTRL_PAGEERASE;
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ptr = (int32u *)(address & MFB_PAGE_MASK_B);
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length = MFB_PAGE_SIZE_W;
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} else if (BYTE_0(eraseType) == CIB_ERASE) {
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eraseOp = FLASH_CTRL_OPTWREN | FLASH_CTRL_OPTERASE;
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ptr = (int32u *)CIB_BOTTOM;
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length = CIB_SIZE_W;
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} else {
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return FIB_ERR_INVALID_TYPE;
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}
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if ((eraseType & DO_ERASE) != 0) {
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enableFlitf();
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FLASH_CTRL = eraseOp;
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if (BYTE_0(eraseType) == MFB_PAGE_ERASE) {
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FLASH_ADDR = (address & MFB_PAGE_MASK_B);
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}
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eraseOp |= FLASH_CTRL_FLA_START;
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// Perform the actual erase.
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FLASH_CTRL = eraseOp;
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// Wait for the busy bit to clear, indicating operation is done.
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while ((FLASH_STATUS & FLASH_STATUS_FLA_BSY) != 0) {}
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// Reset the operation complete flag.
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FLASH_STATUS = FLASH_STATUS_EOP;
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// Check for errors; the only relevant one for erasing is write protection.
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if (FLASH_STATUS & FLASH_STATUS_WRP_ERR) {
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FLASH_STATUS = FLASH_STATUS_WRP_ERR;
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status = FIB_ERR_WRITE_PROTECTED;
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}
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disableFlitf();
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}
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if (status == FIB_SUCCESS
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&& (eraseType & DO_VERIFY) != 0) {
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int32u i;
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for (i = 0; i < length; i++) {
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if (*ptr != 0xFFFFFFFF) {
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return FIB_ERR_VERIFY_FAILED;
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}
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ptr++;
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}
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}
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return status;
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}
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#endif // ST_EMU_TEST
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static boolean verifyFib(void)
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{
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// Ensure that a programmed FIB of a proper version is present
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return ( (halFixedAddressTable.baseTable.type == FIXED_ADDRESS_TABLE_TYPE) &&
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( ( (halFixedAddressTable.baseTable.version & FAT_MAJOR_VERSION_MASK)
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== 0x0000 ) &&
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(halFixedAddressTable.baseTable.version >= 0x0002)
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)
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);
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}
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//The parameter 'eraseType' chooses which erasure will be performed while
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//the 'address' parameter chooses the page to be erased during MFB page erase.
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StStatus halInternalFlashErase(int8u eraseType, int32u address)
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{
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FibStatus status;
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ATOMIC(
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BYPASS_MPU(
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flashEraseIsActive = TRUE;
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#if defined(ST_EMU_TEST)
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// Always try to use the FIB bootloader if its present
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if(verifyFib()) {
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status = halFixedAddressTable.fibFlashErase(
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(((int32u)eraseType) | DO_ERASE),
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address);
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} else {
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status = fibFlashErase((((int32u)eraseType) | DO_ERASE), address);
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}
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#else
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assert(verifyFib());
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status = halFixedAddressTable.fibFlashErase(
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(((int32u)eraseType) | DO_ERASE),
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address);
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#endif
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)
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)
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//If there are any interrupts pending that could have been delayed for 21ms,
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//they will be serviced here since we exit the ATOMIC block. These ISRs
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//can query the flash library and find out that erasing is active. After
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//this point, we're no longer ATOMIC/disrupting latency so our erase
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//active flag should be cleared.
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flashEraseIsActive = FALSE;
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if(status!=FIB_SUCCESS) {
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return fibToStStatus[status];
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}
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#if defined(ST_EMU_TEST)
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// Always try to use the FIB bootloader if its present
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if(verifyFib()) {
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status = halFixedAddressTable.fibFlashErase(
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(((int32u)eraseType) | DO_VERIFY),
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address);
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} else {
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status = fibFlashErase((((int32u)eraseType) | DO_VERIFY), address);
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}
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#else
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status = halFixedAddressTable.fibFlashErase(
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(((int32u)eraseType) | DO_VERIFY),
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address);
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#endif
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return fibToStStatus[status];
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}
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//The parameter 'address' defines the starting address of where the
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//programming will occur - this parameter MUST be half-word aligned since all
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//programming operations are HW. The parameter 'data' is a pointer to a buffer
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//containin the 16bit half-words to be written. Length is the number of 16bit
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//half-words contained in 'data' to be written to flash.
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//NOTE: This function can NOT write the option bytes and will throw an error
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//if that is attempted.
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StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length)
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{
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FibStatus status;
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length = length * 2; // fib routines specify length in bytes
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ATOMIC(
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BYPASS_MPU(
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#if defined(ST_EMU_TEST)
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// Always try to use the FIB bootloader if its present
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if(verifyFib()) {
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status = halFixedAddressTable.fibFlashWrite(address,
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(int8u *)data,
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length,
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0);
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} else {
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status = fibFlashWrite(address, (int8u *)data, length, 0);
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}
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#else
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// Ensure that a programmed FIB of a proper version is present
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assert(verifyFib());
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status = halFixedAddressTable.fibFlashWrite(address,
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(int8u *)data,
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length,
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0);
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#endif
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)
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)
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if(status!=FIB_SUCCESS) {
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return fibToStStatus[status];
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}
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#if defined(ST_EMU_TEST)
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// Always try to use the FIB bootloader if its present
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if(verifyFib()) {
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status = halFixedAddressTable.fibFlashWrite(address,
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(int8u *)data,
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0,
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length);
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} else {
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status = fibFlashWriteVerify(address, (int8u *)data, length);
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}
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#else
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status = halFixedAddressTable.fibFlashWrite(address,
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(int8u *)data,
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0,
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length);
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#endif
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return fibToStStatus[status];
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}
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//The parameter 'byte' is the option byte number to be programmed. This
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//parameter can have a value of 0 through 7. 'data' is the 8bit value to be
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//programmed into the option byte since the hardware will calculate the
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//compliment and program the full 16bit option byte.
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StStatus halInternalCibOptionByteWrite(int8u byte, int8u data)
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{
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int16u dataAndInverse = HIGH_LOW_TO_INT(~data, data);
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// There are only 8 option bytes, don't try to program more than that.
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if (byte > 7) {
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return ST_ERR_FLASH_PROG_FAIL;
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}
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return halInternalFlashWrite(CIB_OB_BOTTOM + (byte << 1), &dataAndInverse, 1);
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}
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