122 lines
3.4 KiB
C
122 lines
3.4 KiB
C
/*
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* Copyright (c) 2007, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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*/
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/**
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* \file
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* DMA interrupt handling.
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* \author
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* Nicolas Tsiftes <nvt@sics.se>
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*/
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#include "contiki.h"
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#include "contiki-msb430.h"
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#include "dev/cc1020.h"
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#include "dev/dma.h"
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#include "isr_compat.h"
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static void (*callbacks[DMA_LINES])(void);
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ISR(DACDMA, irq_dacdma)
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{
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if(DMA0CTL & DMAIFG) {
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DMA0CTL &= ~(DMAIFG | DMAIE);
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if(callbacks[0] != NULL) {
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callbacks[0]();
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}
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_BIC_SR_IRQ(LPM3_bits);
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}
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if(DMA1CTL & DMAIFG) {
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DMA1CTL &= ~(DMAIFG | DMAIE);
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if(callbacks[1] != NULL) {
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callbacks[1]();
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}
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_BIC_SR_IRQ(LPM3_bits);
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}
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if(DMA2CTL & DMAIFG) {
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DMA2CTL &= ~(DMAIFG | DMAIE);
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if(callbacks[2] != NULL) {
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callbacks[2]();
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}
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_BIC_SR_IRQ(LPM3_bits);
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}
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if(DAC12_0CTL & DAC12IFG) {
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DAC12_0CTL &= ~(DAC12IFG | DAC12IE);
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}
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if(DAC12_1CTL & DAC12IFG) {
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DAC12_1CTL &= ~(DAC12IFG | DAC12IE);
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}
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}
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int
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dma_subscribe(int line, void (*callback)(void))
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{
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if(line >= DMA_LINES) {
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return -1;
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}
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callbacks[line] = callback;
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return 0;
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}
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void
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dma_transfer(unsigned char *dst, unsigned char *src, unsigned len)
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{
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/* Configure DMA Channel 0 for UART0 TXIFG. */
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DMACTL0 = DMA0TSEL_4;
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/* No DMAONFETCH, ROUNDROBIN, ENNMI. */
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DMACTL1 = 0x0000;
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/*
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* Set single transfer mode with byte-per-byte transfers.
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*
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* The source address is incremented for each byte, while the
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* destination address remains constant.
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*
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* In order to avoid missing the first rising edge of the trigger
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* signal, it is important to use the level-sensitive trigger when
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* using USART transfer interrupts.
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*/
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DMA0CTL = DMADT_0 | DMADSTINCR_0 | DMASRCINCR_3 | DMASBDB | DMALEVEL;
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DMA0SA = (unsigned) src;
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DMA0DA = (unsigned) dst;
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DMA0SZ = len;
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DMA0CTL |= DMAEN | DMAIE; /* enable DMA and interrupts */
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U0CTL &= ~SWRST; /* enable the UART state machine */
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}
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