412facb831
architecture for the Rime stack for Contiki. The Chameleon architecture separates the header processing from the Rime protocol logic. Instead of having each protocol create its own part of the packet header, protocols use packet attributes. Before sending a packet, a special Chameleon header processing module creates a packet header from the packet attributes. The same Chameleon module parses incoming packets and creates packet attributes from the header. The details are in our SenSys 2007 paper: Adam Dunkels, Fredrik Osterlind, Zhitao He. An Adaptive Communication Architecture for Wireless Sensor Networks. In Proceedings of the Fifth ACM Conference on Networked Embedded Sensor Systems (SenSys 2007), Sydney, Australia, November 2007. http://www.sics.se/~adam/dunkels07adaptive.pdf This is a rewrite of the code that was developed for the paper.
195 lines
5.4 KiB
C
195 lines
5.4 KiB
C
/* -*- C -*- */
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/* @(#)$Id: contiki-conf.h,v 1.25 2008/02/25 02:14:34 adamdunkels Exp $ */
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#ifndef CONTIKI_CONF_H
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#define CONTIKI_CONF_H
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#define RIMEBUF_CONF_ATTRS_INLINE 1
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#define SHELL_VARS_CONF_RAM_BEGIN 0x1100
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#define SHELL_VARS_CONF_RAM_END 0x2000
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#define TIMESYNCH_CONF_ENABLED 1
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#define SIMPLE_CC2420_CONF_TIMESTAMPS 1
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#define PROFILE_CONF_ON 0
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#define ENERGEST_CONF_ON 1
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#define HAVE_STDINT_H
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#include "msp430def.h"
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#ifndef RF_CHANNEL
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#define RF_CHANNEL 26
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#endif /* RF_CHANNEL */
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#define ELFLOADER_CONF_DATAMEMORY_SIZE 0x800
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#define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x1000
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#define IRQ_PORT1 0x01
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#define IRQ_PORT2 0x02
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#define IRQ_ADC 0x03
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#define CCIF
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#define CLIF
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#define CC_CONF_INLINE inline
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#define AODV_COMPLIANCE
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#define AODV_NUM_RT_ENTRIES 32
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#define TMOTE_SKY 1
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#define WITH_ASCII 1
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#define PROCESS_CONF_NUMEVENTS 8
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#define PROCESS_CONF_STATS 1
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/*#define PROCESS_CONF_FASTPOLL 4*/
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/* CPU target speed in Hz */
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#define F_CPU 2457600uL
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/* Our clock resolution, this is the same as Unix HZ. */
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#define CLOCK_CONF_SECOND 64
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#define BAUD2UBR(baud) ((F_CPU/baud))
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#define UIP_CONF_ICMP_DEST_UNREACH 1
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#define UIP_CONF_DHCP_LIGHT
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#define UIP_CONF_LLH_LEN 0
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#define UIP_CONF_BUFFER_SIZE 110
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#define UIP_CONF_RECEIVE_WINDOW (UIP_CONF_BUFFER_SIZE - 40)
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#define UIP_CONF_MAX_CONNECTIONS 4
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#define UIP_CONF_MAX_LISTENPORTS 8
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#define UIP_CONF_UDP_CONNS 12
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#define UIP_CONF_FWCACHE_SIZE 30
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#define UIP_CONF_BROADCAST 1
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#define UIP_ARCH_IPCHKSUM 1
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#define UIP_CONF_UDP_CHECKSUMS 1
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#define UIP_CONF_PINGADDRCONF 0
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#define UIP_CONF_LOGGING 0
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#define UIP_CONF_TCP_SPLIT 0
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/*
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* Definitions below are dictated by the hardware and not really
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* changeable!
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*/
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/* LED ports */
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#define LEDS_PxDIR P5DIR
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#define LEDS_PxOUT P5OUT
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#define LEDS_CONF_RED 0x10
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#define LEDS_CONF_GREEN 0x20
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#define LEDS_CONF_YELLOW 0x40
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/* Button sensors. */
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#define IRQ_PORT2 0x02
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typedef unsigned short uip_stats_t;
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typedef unsigned short clock_time_t;
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typedef unsigned long off_t;
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#define ROM_ERASE_UNIT_SIZE 512
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#define XMEM_ERASE_UNIT_SIZE (64*1024L)
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/* Use the first 64k of external flash for node configuration */
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#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
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/* Use the second 64k of external flash for codeprop. */
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#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_RAM_CONF_SIZE 4096
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#define CC2420_RADIO
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/*
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* SPI bus configuration for the TMote Sky.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF U0TXBUF
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#define SPI_RXBUF U0RXBUF
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/* USART0 Tx buffer ready? */
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#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
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/* USART0 Rx buffer ready? */
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#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
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#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
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#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
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#define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
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/*
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* SPI bus - M25P80 external flash configuration.
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*/
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#define FLASH_PWR 3 /* P4.3 Output */
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#define FLASH_CS 4 /* P4.4 Output */
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#define FLASH_HOLD 7 /* P4.7 Output */
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/* Enable/disable flash access to the SPI bus (active low). */
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#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
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#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
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#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
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#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
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/*
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* SPI bus - CC2420 pin configuration.
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*/
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#define FIFO_P 0 /* P1.0 - Input: FIFOP from CC2420 */
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#define FIFO 3 /* P1.3 - Input: FIFO from CC2420 */
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#define CCA 4 /* P1.4 - Input: CCA from CC2420 */
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#define SFD 1 /* P4.1 - Input: SFD from CC2420 */
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#define CSN 2 /* P4.2 - Output: SPI Chip Select (CS_N) */
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#define VREG_EN 5 /* P4.5 - Output: VREG_EN to CC2420 */
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#define RESET_N 6 /* P4.6 - Output: RESET_N to CC2420 */
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/* Pin status. */
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#define FIFO_IS_1 (!!(P1IN & BV(FIFO)))
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#define CCA_IS_1 (!!(P1IN & BV(CCA) ))
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#define RESET_IS_1 (!!(P4IN & BV(RESET_N)))
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#define VREG_IS_1 (!!(P4IN & BV(VREG_EN)))
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#define FIFOP_IS_1 (!!(P1IN & BV(FIFO_P)))
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#define SFD_IS_1 (!!(P4IN & BV(SFD)))
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/* The CC2420 reset pin. */
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#define SET_RESET_INACTIVE() ( P4OUT |= BV(RESET_N) )
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#define SET_RESET_ACTIVE() ( P4OUT &= ~BV(RESET_N) )
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/* CC2420 voltage regulator enable pin. */
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#define SET_VREG_ACTIVE() ( P4OUT |= BV(VREG_EN) )
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#define SET_VREG_INACTIVE() ( P4OUT &= ~BV(VREG_EN) )
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/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
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#define FIFOP_INT_INIT() do {\
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P1IES &= ~BV(FIFO_P);\
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CLEAR_FIFOP_INT();\
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} while (0)
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/* FIFOP on external interrupt 0. */
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#define ENABLE_FIFOP_INT() do { P1IE |= BV(FIFO_P); } while (0)
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#define DISABLE_FIFOP_INT() do { P1IE &= ~BV(FIFO_P); } while (0)
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#define CLEAR_FIFOP_INT() do { P1IFG &= ~BV(FIFO_P); } while (0)
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/* Enables/disables CC2420 access to the SPI bus (not the bus).
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*
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* These guys should really be renamed but are compatible with the
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* original Chipcon naming.
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*
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* SPI_CC2420_ENABLE/SPI_CC2420_DISABLE???
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* CC2420_ENABLE_SPI/CC2420_DISABLE_SPI???
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*/
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#define SPI_ENABLE() ( P4OUT &= ~BV(CSN) ) /* ENABLE CSn (active low) */
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#define SPI_DISABLE() ( P4OUT |= BV(CSN) ) /* DISABLE CSn (active low) */
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#endif /* CONTIKI_CONF_H */
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