272 lines
8.0 KiB
C
272 lines
8.0 KiB
C
/*
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* Copyright (c) 2007, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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*/
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/**
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* \file
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* AVR-specific rtimer code
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* Defaults to Timer3 for those ATMEGAs that have it.
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* If Timer3 not present Timer1 will be used.
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* \author
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* Fredrik Osterlind <fros@sics.se>
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* Joakim Eriksson <joakime@sics.se>
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*/
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/* OBS: 8 seconds maximum time! */
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <stdio.h>
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#include "sys/energest.h"
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#include "sys/rtimer.h"
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#include "rtimer-arch.h"
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/* Track flow through rtimer interrupts*/
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#if DEBUGFLOWSIZE&&0
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extern uint8_t debugflowsize,debugflow[DEBUGFLOWSIZE];
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#define DEBUGFLOW(c) if (debugflowsize<(DEBUGFLOWSIZE-1)) debugflow[debugflowsize++]=c
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#else
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#define DEBUGFLOW(c)
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#endif
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/*---------------------------------------------------------------------------*/
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#if RTIMER_ARCH_PRESCALER
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ISR (PLAT_VECT) {
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DEBUGFLOW('/');
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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/* Disable rtimer interrupts */
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PLAT_TIMSK &=
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~( (1 << PLAT_OCIEA)
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| (1 << PLAT_OCIEB)
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| (1 << PLAT_OCIEC)
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| (1 << PLAT_TOIE)
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| (1 << PLAT_ICIE)
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);
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#if RTIMER_CONF_NESTED_INTERRUPTS
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/* Enable nested interrupts. Allows radio interrupt during rtimer interrupt. */
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/* All interrupts are enabled including recursive rtimer, so use with caution */
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sei();
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#endif
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/* Call rtimer callback */
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rtimer_run_next();
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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DEBUGFLOW('\\');
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}
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#endif
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/*---------------------------------------------------------------------------*/
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void
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rtimer_arch_init(void)
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{
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#if RTIMER_ARCH_PRESCALER
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/* Disable interrupts (store old state) */
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uint8_t sreg;
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sreg = SREG;
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cli ();
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/* Disable all timer functions */
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PLAT_TIMSK &=
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~( (1 << PLAT_OCIEA)
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| (1 << PLAT_OCIEB)
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| (1 << PLAT_OCIEC)
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| (1 << PLAT_TOIE)
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| (1 << PLAT_ICIE)
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);
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/* Write 1s to clear existing timer function flags */
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PLAT_TIFR |=
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( (1 << PLAT_ICF)
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| (1 << PLAT_OCFA)
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| (1 << PLAT_OCFB)
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| (1 << PLAT_OCFC)
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| (1 << PLAT_TOV)
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);
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/* Default timer behaviour */
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PLAT_TCCRA = 0;
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PLAT_TCCRB = 0;
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PLAT_TCCRC = 0;
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/* Reset counter */
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PLAT_TCNT = 0;
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#if RTIMER_ARCH_PRESCALER==1024
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PLAT_TCCRB |= 5;
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#elif RTIMER_ARCH_PRESCALER==256
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PLAT_TCCRB |= 4;
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#elif RTIMER_ARCH_PRESCALER==64
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PLAT_TCCRB |= 3;
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#elif RTIMER_ARCH_PRESCALER==8
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PLAT_TCCRB |= 2;
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#elif RTIMER_ARCH_PRESCALER==1
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PLAT_TCCRB |= 1;
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#else
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#error Timer PRESCALER factor not supported.
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#endif
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/* Restore interrupt state */
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SREG = sreg;
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#endif /* RTIMER_ARCH_PRESCALER */
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}
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/*---------------------------------------------------------------------------*/
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void
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rtimer_arch_schedule(rtimer_clock_t t)
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{
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#if RTIMER_ARCH_PRESCALER
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/* Disable interrupts (store old state) */
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uint8_t sreg;
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sreg = SREG;
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cli ();
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DEBUGFLOW(':');
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/* Set compare register */
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PLAT_OCRA = t;
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/* Write 1s to clear all timer function flags */
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PLAT_TIFR |=
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( (1 << PLAT_ICF)
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| (1 << PLAT_OCFA)
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| (1 << PLAT_OCFB)
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| (1 << PLAT_OCFC)
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| (1 << PLAT_TOV)
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);
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/* Enable interrupt on OCRXA match */
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PLAT_TIMSK |= (1 << PLAT_OCIEA);
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/* Restore interrupt state */
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SREG = sreg;
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#endif /* RTIMER_ARCH_PRESCALER */
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}
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#if RDC_CONF_MCU_SLEEP
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/*---------------------------------------------------------------------------*/
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void
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rtimer_arch_sleep(rtimer_clock_t howlong)
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{
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/* Deep Sleep for howlong rtimer ticks. This will stop all timers except
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* for TIMER2 which can be clocked using an external crystal.
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* Unfortunately this is an 8 bit timer; a lower prescaler gives higher
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* precision but smaller maximum sleep time.
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* Here a maximum 128msec (contikimac 8Hz channel check sleep) is assumed.
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* The rtimer and system clocks are adjusted to reflect the sleep time.
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*/
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#include <avr/sleep.h>
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#include <dev/watchdog.h>
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uint32_t longhowlong;
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#if AVR_CONF_USE32KCRYSTAL
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/* Save TIMER2 configuration if clock.c is using it */
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uint8_t savedTCNT2=TCNT2, savedTCCR2A=TCCR2A, savedTCCR2B = TCCR2B, savedOCR2A = OCR2A;
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#endif
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cli();
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watchdog_stop();
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set_sleep_mode(SLEEP_MODE_PWR_SAVE);
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/* Set TIMER2 clock asynchronus from external source, CTC mode */
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ASSR |= (1 << AS2);
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TCCR2A =(1<<WGM21);
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/* Set prescaler and TIMER2 output compare register */
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#if 0 //Prescale by 1024 - 32 ticks/sec, 8 seconds max sleep
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TCCR2B =((1<<CS22)|(1<<CS21)|(1<<CS20));
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longhowlong=howlong*32UL;
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#elif 0 // Prescale by 256 - 128 ticks/sec, 2 seconds max sleep
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TCCR2B =((1<<CS22)|(1<<CS21)|(0<<CS20));
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longhowlong=howlong*128UL;
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#elif 0 // Prescale by 128 - 256 ticks/sec, 1 seconds max sleep
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TCCR2B =((1<<CS22)|(0<<CS21)|(1<<CS20));
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longhowlong=howlong*256UL;
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#elif 0 // Prescale by 64 - 512 ticks/sec, 500 msec max sleep
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TCCR2B =((1<<CS22)|(0<<CS21)|(0<<CS20));
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longhowlong=howlong*512UL;
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#elif 1 // Prescale by 32 - 1024 ticks/sec, 250 msec max sleep
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TCCR2B =((0<<CS22)|(1<<CS21)|(1<<CS20));
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longhowlong=howlong*1024UL;
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#elif 0 // Prescale by 8 - 4096 ticks/sec, 62.5 msec max sleep
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TCCR2B =((0<<CS22)|(1<<CS21)|(0<<CS20));
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longhowlong=howlong*4096UL;
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#else // No Prescale - 32768 ticks/sec, 7.8 msec max sleep
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TCCR2B =((0<<CS22)|(0<<CS21)|(1<<CS20));
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longhowlong=howlong*32768UL;
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#endif
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OCR2A = longhowlong/RTIMER_ARCH_SECOND;
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/* Reset timer count, wait for the write (which assures TCCR2x and OCR2A are finished) */
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TCNT2 = 0;
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while(ASSR & (1 << TCN2UB));
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/* Enable TIMER2 output compare interrupt, sleep mode and sleep */
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TIMSK2 |= (1 << OCIE2A);
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SMCR |= (1 << SE);
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sei();
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ENERGEST_OFF(ENERGEST_TYPE_CPU);
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if (OCR2A) sleep_mode();
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//...zzZZZzz...Ding!//
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/* Disable sleep mode after wakeup, so random code cant trigger sleep */
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SMCR &= ~(1 << SE);
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/* Adjust rtimer ticks if rtimer is enabled. TIMER3 is preferred, else TIMER1 */
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#if RTIMER_ARCH_PRESCALER
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PLAT_TCNT += howlong;
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#endif
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ENERGEST_ON(ENERGEST_TYPE_CPU);
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#if AVR_CONF_USE32KCRYSTAL
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/* Restore clock.c configuration */
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cli();
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TCCR2A = savedTCCR2A;
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TCCR2B = savedTCCR2B;
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OCR2A = savedOCR2A;
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TCNT2 = savedTCNT2;
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sei();
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#else
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/* Disable TIMER2 interrupt */
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TIMSK2 &= ~(1 << OCIE2A);
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#endif
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watchdog_start();
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/* Adjust clock.c for the time spent sleeping */
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longhowlong=CLOCK_CONF_SECOND;
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longhowlong*=howlong;
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clock_adjust_ticks(longhowlong/RTIMER_ARCH_SECOND);
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}
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#if !AVR_CONF_USE32KCRYSTAL
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/*---------------------------------------------------------------------------*/
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/* TIMER2 Interrupt service */
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ISR(TIMER2_COMPA_vect)
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{
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// TIMSK2 &= ~(1 << OCIE2A); //Just one interrupt needed for waking
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}
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#endif /* !AVR_CONF_USE32KCRYSTAL */
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#endif /* RDC_CONF_MCU_SLEEP */
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