PCI Interrupt Routing is mapped using Interrupt Queue Agents
IRQAGENT[0:3] and aggregating the INT[A:D] interrupts for each
PCI-mapped device in the SoC.
PCI based interrupts PIRQ[A:H] are then available for consumption
by either the 8259 PICs or the IO-APIC, depending on the configuration
of the 8 PIRQx Routing Control Registers PIRQ[A:H].
More information about can be find in Intel Quark X1000 datasheet[1]
section 21.11.
[1] - http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html
This patch adds a generic device driver structure with a field for
referencing an MMIO range. It also provides a structure
initialization procedure that initializes the MMIO range field with
the value read from the PCI BAR0 register for a device.
This patch adds the pci.c and pci.h files, which support access to PCI
configuration registers through a function interface. It defines the
PCI configuration register access I/O port addresses and the
pci_config_addr union and structure to assist in specifying addresses
of PCI configuration registers. It also defines the PCI configuration
register identifier for PCI BAR0.
This patch also adds wrappers for 32-bit 'in' and 'out' port I/O
instructions. They were placed in helpers.S, since they may be useful
to other modules besides just the PCI support module.
