The DNS resolver requires 1/4 sec clock resolution. The retro targets had a 1/2 sec clock resolution (optimized for the 1/2 sec TCP timer) resulting in DNS resolver timeouts being 0. Therefore the retro target clock resolution is now increased to 1/4 sec.
When a client sends a CoAP request with no block2 size,
the default one would be set to REST_MAX_CHUNK_SIZE.
However, this is not guaranteed to be a power of 2.
This can lead to clients receiving a bigger payload than expected as
part of the header, and ending up with duplicated content.
Setting the default to COAP_MAX_BLOCK_SIZE,
which is guaranteed to be a power of 2, fixes this.
Only odd addresses may be programmed to the ERXRDPT registers, so
initialize them to RX_BUF_END instead of RX_BUF_START.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The Bit Field Set and Bit Field Clear commands are more efficient than
the Read Control Register + Write Control Register combination, so use
them whenever possible, i.e. for the ETH registers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This only applies to half duplex, so the actual configuration of MACON4
does not need to be changed.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The register 0x01 in bank 2, named MACON2 in the code, is actually
reserved, so its contents must not be changed.
This register has been marked as reserved from the revision B of the
data sheet in July 2006. The current revision of the data sheet is E,
and it is quite clear about this register.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This is useful as debug information since the revisions of this device
have notable differences.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
A delay of 1 ms must be added after the System Reset Command. Still wait
for ESTAT.CLKRDY afterwards as a precaution.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The Read Control Register command requires that a dummy byte be read
before the register value for the MAC and MII registers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The read/writedatabyte() functions are just a special case of
read/writedata() with a simpler API, so reuse these instead of
duplicating code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
../..//core/net/mac/contikimac/contikimac.c:503:11: warning: variable
‘seqno’ set but not used [-Wunused-but-set-variable]
../..//core/net/mac/contikimac/contikimac.c:496:7: warning: variable
‘len’ set but not used [-Wunused-but-set-variable]
Both of these variables are only used if RDC_CONF_HARDWARE_ACK is not
true.
Their definitions and use have been moved into #ifdef guards so they do
not appear if RDC_CONF_HARDWARE_ACK is set.
Allow the project / platform to provide values for CCA_SLEEP_TIME and LISTEN_TIME_AFTER_PACKET_DETECTED.
This is useful for sub-ghz operation.
This has been shamelessly stolen from the [Mountain Sensing project](https://github.com/feshie/contiki)
@heliosfa @kmartinez
There are scenarios in which it is beneficial to search for an Etherne chip at several i/o locations. To do so the chip initialization is performed at several i/o locations until it succeeds. In order to allow for that operation model the i/o location fixup needs to be repeatable.
Note: This won't work with the RR-Net because the fixup bits overlap with the chip i/o bits.
Instead of hard coded setting the resend timer to CLOCK_SECOND,
restart it, so that the time between ANY following transmissions will
be as passed to stunicast_send_stubborn.
