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12 commits

Author SHA1 Message Date
Michael LeMay 4cdb7ba9b6 x86: Add TSS-based protection domain support
This patch extends the protection domain framework with an additional
plugin to use Task-State Segment (TSS) structures to offload much of
the work of switching protection domains to the CPU.  This can save
space compared to paging, since paging requires two 4KiB page tables
and one 32-byte page table plus one whole-system TSS and an additional
32-byte data structure for each protection domain, whereas the
approach implemented by this patch just requires a 128-byte data
structure for each protection domain.  Only a small number of
protection domains will typically be used, so
n * 128 < 8328 + (n * 32).

For additional information, please refer to cpu/x86/mm/README.md.

GCC 6 is introducing named address spaces for the FS and GS segments
[1].  LLVM Clang also provides address spaces for the FS and GS
segments [2].  This patch also adds support to the multi-segment X86
memory management subsystem for using these features instead of inline
assembly blocks, which enables type checking to detect some address
space mismatches.

[1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html
[2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
2016-04-22 08:16:39 -07:00
Michael LeMay 3908253038 x86: Add support for (paging-based) protection domains
This patch implements a simple, lightweight form of protection domains
using a pluggable framework.  Currently, the following plugin is
available:

 - Flat memory model with paging.

The overall goal of a protection domain implementation within this
framework is to define a set of resources that should be accessible to
each protection domain and to prevent that protection domain from
accessing other resources.  The details of each implementation of
protection domains may differ substantially, but they should all be
guided by the principle of least privilege.  However, that idealized
principle is balanced against the practical objectives of limiting the
number of relatively time-consuming context switches and minimizing
changes to existing code.

For additional information, please refer to cpu/x86/mm/README.md.

This patch also causes the C compiler to be used as the default linker
and assembler.
2016-03-21 17:18:06 -07:00
Michael LeMay c815fa4511 x86: Use shared ISR for I2C and GPIO
This patch permits interrupts to be generated by both the I2C and GPIO
controllers for simultaneously-executing applications. The controllers
share a single interrupt pin, INTC. Prior to this patch,
quarkX1000_gpio_init() routed INTA to PIRQC and IRQ 10 (due to an
incorrect assumption that INTA is connected to the GPIO controller),
and quarkX1000_i2c_init() routed INTC to PIRQC and IRQ 9. The I2C
controller initialization is a prerequisite for GPIO initialization,
so the final configuration was that INTA and INTC were both routed to
PIRQC and IRQ 10. Thus, only the GPIO ISR was being invoked, even if
the I2C controller was actually responsible for the interrupt.

This patch refactors the I2C and GPIO ISR setup and handler code so
that the shared portions are combined in
cpu/x86/drivers/legacy_pc/shared-isr.[ch].  The I2C and GPIO drivers
communicate their interrupt information to the shared component by
placing structures in a specific section of the binary.
2016-02-16 21:19:44 -08:00
Michael LeMay abeed93da5 x86: Add driver for Intel Quark X1000 built-in Ethernet
This patch adds a simple, space-efficient driver for the Ethernet
interface built into the Intel Quark X1000.  It only allocates a
single packet descriptor for each of the transmit and receive
directions, computes checksums on the CPU, and enables
store-and-forward mode for both transmit and receive directions.
2015-12-21 08:06:14 -02:00
Ricardo de Almeida Gonzaga 60f6edef80 x86: Add support for PCI BAR1
This patch adds support for PCI BAR1 and also changes
the pci_init(), instead of having one function for each `bar`
we now set the `bar` to pci_config_addr_t parameter before calling
the pci_init() function..
2015-12-21 08:06:14 -02:00
Michael LeMay 6dc27579bc x86: Extend PCI driver module with support for metadata and configuration writes
This patch adds the 'meta' field to the generic driver structure to
point to optional driver-defined metadata.  It also modifies the
associated initialization routine to populate it and updates the 16X50
UART driver to use the new initialization routine signature.  This
patch also adds a function to perform PCI configuration register
writes, definitions for the PCI Command configuration register address
and some of the bits in that register, and a function to set
additional bits in that register.  Finally, it adds macros to help
with performing MMIO to and from PCI devices.
2015-12-21 08:06:14 -02:00
Ricardo de Almeida Gonzaga c796e270bf x86: Add Intel Quark X1000 PCI Interrupt Routing support
PCI Interrupt Routing is mapped using Interrupt Queue Agents
IRQAGENT[0:3] and aggregating the INT[A:D] interrupts for each
PCI-mapped device in the SoC.

PCI based interrupts PIRQ[A:H] are then available for consumption
by either the 8259 PICs or the IO-APIC, depending on the configuration
of the 8 PIRQx Routing Control Registers PIRQ[A:H].

More information about can be find in Intel Quark X1000 datasheet[1]
section 21.11.

[1] - http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html
2015-12-21 08:06:14 -02:00
Michael LeMay 6acdf50262 x86: Add driver for MMIO-accessible 16X50 UART
This patch adds a driver for an MMIO-accessible 16X50 UART.  It
assumes that the boot firmware assigned an MMIO range to the UART.  It
operates in polled mode with FIFOs enabled.
2015-12-21 08:06:14 -02:00
Michael LeMay c5f9cefac7 x86: Add generic driver structure and associated initialization code
This patch adds a generic device driver structure with a field for
referencing an MMIO range.  It also provides a structure
initialization procedure that initializes the MMIO range field with
the value read from the PCI BAR0 register for a device.
2015-12-21 08:06:14 -02:00
Michael LeMay 2dccb55e15 x86: Add PCI support
This patch adds the pci.c and pci.h files, which support access to PCI
configuration registers through a function interface.  It defines the
PCI configuration register access I/O port addresses and the
pci_config_addr union and structure to assist in specifying addresses
of PCI configuration registers.  It also defines the PCI configuration
register identifier for PCI BAR0.

This patch also adds wrappers for 32-bit 'in' and 'out' port I/O
instructions.  They were placed in helpers.S, since they may be useful
to other modules besides just the PCI support module.
2015-12-21 08:06:14 -02:00
Andre Guedes cb0510ebcf x86: Disable NMI while initializing RTC
According to [1], we should disable non-maskable and maskable interrupts
while initializing RTC. Otherwise, the RTC may be left in an undefined
state (non-functional) if an interrupt occurs. Currently, maskable
interrupts are already disabled, but NMI is not.

This patch adds helpers APIs to enable/disable non-maskable interrupts
(NMI) and changes rtc_init() to disable NMI while initializing the RTC.

NMI enable/disable code is legacy-PC specific therefore it was put in
driver/legacy_pc/ directory.

Regarding the RTC initialization changes, just calling nmi_disable() and
nmi_enable is not enough since NMI and RTC share the same IO port. So We
should also set the NMI_ENABLE bit while selecting the RTC_INDEX.

Additionally, the nmi_disable() call is not strictly required since we
set the NMI_ENABLE bit while selecting the RTC_INDEX. However, to make
clear hat we are disabling NMI and to improve readability (by matching
NMI disable/enable), the nmi_disable() call was purposely used.

[1] http://wiki.osdev.org/RTC
2015-12-21 08:06:14 -02:00
Jesus Sanchez-Palencia 23e8090257 x86: Move available drivers into drivers/legacy_pc/
All drivers implemented so far are for chips which are only available
on legacy x86 PCs. This commit moves them into a more appropriate folder,
also making the cpu/x86/drivers/ folder ready for other x86 based SoCs.
2015-12-21 08:06:14 -02:00