This patch extends the protection domain framework with an additional
plugin to use Task-State Segment (TSS) structures to offload much of
the work of switching protection domains to the CPU. This can save
space compared to paging, since paging requires two 4KiB page tables
and one 32-byte page table plus one whole-system TSS and an additional
32-byte data structure for each protection domain, whereas the
approach implemented by this patch just requires a 128-byte data
structure for each protection domain. Only a small number of
protection domains will typically be used, so
n * 128 < 8328 + (n * 32).
For additional information, please refer to cpu/x86/mm/README.md.
GCC 6 is introducing named address spaces for the FS and GS segments
[1]. LLVM Clang also provides address spaces for the FS and GS
segments [2]. This patch also adds support to the multi-segment X86
memory management subsystem for using these features instead of inline
assembly blocks, which enables type checking to detect some address
space mismatches.
[1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html
[2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
This patch implements a simple, lightweight form of protection domains
using a pluggable framework. Currently, the following plugin is
available:
- Flat memory model with paging.
The overall goal of a protection domain implementation within this
framework is to define a set of resources that should be accessible to
each protection domain and to prevent that protection domain from
accessing other resources. The details of each implementation of
protection domains may differ substantially, but they should all be
guided by the principle of least privilege. However, that idealized
principle is balanced against the practical objectives of limiting the
number of relatively time-consuming context switches and minimizing
changes to existing code.
For additional information, please refer to cpu/x86/mm/README.md.
This patch also causes the C compiler to be used as the default linker
and assembler.
This patch configures Isolated Memory Regions (IMRs) to block DMA to
code and data regions that do not contain any data that needs to be
DMA-accessible.
The Intel Quark X1000 SoC includes support for Isolated Memory Regions
(IMRs), which are specified using range registers and associated
control registers that are accessible via the message bus. This patch
adds a driver for accessing those registers.
The Intel Quark X1000 SoC includes a message bus that is accessible
via PCI configuration registers. It communicates to various SoC
components such as the Isolated Memory Region (IMR) registers and the
Remote Management Unit. This patch adds a driver for accessing the
message bus.
This patch revises the I2C and GPIO initialization code to always be
run during platform boot rather than within each process that requires
it.
This patch also revises the gpio-output example to use a pin that is
set as an output by the default pinmux configuration. Previously, it
used a pin that was set as an output by the pinmux configuration that
is in effect when the OS does not change the pinmux configuration.
This patch permits interrupts to be generated by both the I2C and GPIO
controllers for simultaneously-executing applications. The controllers
share a single interrupt pin, INTC. Prior to this patch,
quarkX1000_gpio_init() routed INTA to PIRQC and IRQ 10 (due to an
incorrect assumption that INTA is connected to the GPIO controller),
and quarkX1000_i2c_init() routed INTC to PIRQC and IRQ 9. The I2C
controller initialization is a prerequisite for GPIO initialization,
so the final configuration was that INTA and INTC were both routed to
PIRQC and IRQ 10. Thus, only the GPIO ISR was being invoked, even if
the I2C controller was actually responsible for the interrupt.
This patch refactors the I2C and GPIO ISR setup and handler code so
that the shared portions are combined in
cpu/x86/drivers/legacy_pc/shared-isr.[ch]. The I2C and GPIO drivers
communicate their interrupt information to the shared component by
placing structures in a specific section of the binary.
This patch refactors the MMIO routines in the GPIO and I2C drivers to
eliminate the base_addr parameter that specifies the MMIO base
address. Instead, just the MMIO routines themselves retrieve the base
address from the driver structure.
This patch adds a simple, space-efficient driver for the Ethernet
interface built into the Intel Quark X1000. It only allocates a
single packet descriptor for each of the transmit and receive
directions, computes checksums on the CPU, and enables
store-and-forward mode for both transmit and receive directions.
This patch adds gpio-pcal9535a.c and gpio-pcal9535a.h files,
which support access to I2C-based PCAL9535A GPIO controller
configuration register through a function interface.
The PCAL9535A is a low-voltage 16-bit GPIO expander with interrupt
and reset for I2C-bus/SMBus applications. It contains the PCA9535
register set of four pairs of 8-bit Configuration, Input, Output,
and Polarity Inversion registers, and additionally, the PCAL9535A has
Agile I/O, which are additional features specifically designed to
enhance the I/O. More about PCAL9535A can be found in its datasheet[1].
This driver is needed in order to configure Galileo pinmux.
[1] - http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf
This patch adds the i2c.c, i2c.h and i2c-registers.h files,
which support access to I2C controller configuration register
through a function interface.
This patch adds the gpio.c and gpio.h files, which support
access to GPIO Controller (non-legacy) configuration register
through a function interface.
It doesn't add interrupt support due to pinmux reasons. On
Galileo Gen 2 we need to configure a pin as input/interrupt
using pinmux and this can only be achieved through I2C. There's
one pin exported by default as GPIO output and we used this one
to test this driver.
In the future, we plan to add an I2C driver and a pinmux configuration
driver in order to solve this kind of problems.
This patch adds support for PCI BAR1 and also changes
the pci_init(), instead of having one function for each `bar`
we now set the `bar` to pci_config_addr_t parameter before calling
the pci_init() function..
This patch adds the 'meta' field to the generic driver structure to
point to optional driver-defined metadata. It also modifies the
associated initialization routine to populate it and updates the 16X50
UART driver to use the new initialization routine signature. This
patch also adds a function to perform PCI configuration register
writes, definitions for the PCI Command configuration register address
and some of the bits in that register, and a function to set
additional bits in that register. Finally, it adds macros to help
with performing MMIO to and from PCI devices.
PCI Interrupt Routing is mapped using Interrupt Queue Agents
IRQAGENT[0:3] and aggregating the INT[A:D] interrupts for each
PCI-mapped device in the SoC.
PCI based interrupts PIRQ[A:H] are then available for consumption
by either the 8259 PICs or the IO-APIC, depending on the configuration
of the 8 PIRQx Routing Control Registers PIRQ[A:H].
More information about can be find in Intel Quark X1000 datasheet[1]
section 21.11.
[1] - http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html
This patch adds a driver for an MMIO-accessible 16X50 UART. It
assumes that the boot firmware assigned an MMIO range to the UART. It
operates in polled mode with FIFOs enabled.
This patch adds a generic device driver structure with a field for
referencing an MMIO range. It also provides a structure
initialization procedure that initializes the MMIO range field with
the value read from the PCI BAR0 register for a device.
This patch adds the pci.c and pci.h files, which support access to PCI
configuration registers through a function interface. It defines the
PCI configuration register access I/O port addresses and the
pci_config_addr union and structure to assist in specifying addresses
of PCI configuration registers. It also defines the PCI configuration
register identifier for PCI BAR0.
This patch also adds wrappers for 32-bit 'in' and 'out' port I/O
instructions. They were placed in helpers.S, since they may be useful
to other modules besides just the PCI support module.
According to [1], we should disable non-maskable and maskable interrupts
while initializing RTC. Otherwise, the RTC may be left in an undefined
state (non-functional) if an interrupt occurs. Currently, maskable
interrupts are already disabled, but NMI is not.
This patch adds helpers APIs to enable/disable non-maskable interrupts
(NMI) and changes rtc_init() to disable NMI while initializing the RTC.
NMI enable/disable code is legacy-PC specific therefore it was put in
driver/legacy_pc/ directory.
Regarding the RTC initialization changes, just calling nmi_disable() and
nmi_enable is not enough since NMI and RTC share the same IO port. So We
should also set the NMI_ENABLE bit while selecting the RTC_INDEX.
Additionally, the nmi_disable() call is not strictly required since we
set the NMI_ENABLE bit while selecting the RTC_INDEX. However, to make
clear hat we are disabling NMI and to improve readability (by matching
NMI disable/enable), the nmi_disable() call was purposely used.
[1] http://wiki.osdev.org/RTC
All drivers implemented so far are for chips which are only available
on legacy x86 PCs. This commit moves them into a more appropriate folder,
also making the cpu/x86/drivers/ folder ready for other x86 based SoCs.
This commit implements pic_eoi(int irq) and a helper macro PIC_INT(irq).
This first checks which PICs should be 'acked' given an IRQ number, while
the macro returns the actual system interrupt number for the IRQ according
to the offset used on the PIC initialization.
This patch implements the pic_unmask_irq() helper and uses it where
applicable. This function zeros the corresponding bit from the IRQ
number in IMR register.
This patch doesn't implement the pic_mask_irq() helper since it is not
useful at this moment.
This patch adds a driver for the 8254 Programmable Interrupt Timer (PIT).
The driver introduced by this patch programs the PIT to generate interrupt
periodically. The interrupt frequency can be configured by the user.
On each PIT interrupt, a callback configured by the user is called. As
expected, that callback is executed in interrupt context so the user
should be aware of what it is not supposed to do (e.g. to call blocking
functions).
Issues marked as FIXME are all related to missing APIs on the PIC driver
so they will be addressed by a future commit.
This patch adds a driver for Real-Time Clock (RTC). The RTC timer is
suitable to implement some operating system features such as the
system clock. Actually, the RTC will be used to implement the system
clock in galileo platform.
The driver introduced by this patch programs the RTC to generate
interrupt periodically. The interrupt frequency can be configured by the
user. On each RTC interrupt, a callback configured by the user is called.
As expected, that callback is executed in interrupt context so the user
should be aware of what it is not supposed to do (e.g. to call blocking
functions).
This patch also adds the inb() helper function to helpers.h. The helpers
is a wrapper for assembly 'in' instruction.
The Programmable Interrupt Controller is a chip responsible for
translating hardware interrupts to system interrupts. When it
receives an Interrupt Request (IRQ), it triggers the appropriate
interrupt line reaching the appropriate IDT gate, following a
previously setup offset.
There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2
handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance,
would trigger the interrupt 0, clashing with the "Division by zero exception"
handler. Thus the IRQs must be remapped.
This patch implements the PICs initialization through their 4
Initialization Command Words (ICWs) in a very "canonical" way:
- ICW1: the initializing command;
- ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions);
- ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2);
- ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave).
It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially.
These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1
would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n.
As stated, this is an implementation of the legacy 8259 PIC. More
investigation is needed so we decide if it is enough or if we need
the (newer) APIC implementation instead.
This patch also adds the outb() helper function to helpers.h. The helpers
is a wrapper for assembly 'out' instruction.
Finally, since we now properly support hardware interrupts, this patch
also enables IRQs in platform main().
More information:
- Quark X1000 Datasheet, section 21.12, page 898.
- http://wiki.osdev.org/8259_PIC
- http://stanislavs.org/helppc/8259.html
