The Bit Field Set and Bit Field Clear commands are more efficient than
the Read Control Register + Write Control Register combination, so use
them whenever possible, i.e. for the ETH registers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This only applies to half duplex, so the actual configuration of MACON4
does not need to be changed.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The register 0x01 in bank 2, named MACON2 in the code, is actually
reserved, so its contents must not be changed.
This register has been marked as reserved from the revision B of the
data sheet in July 2006. The current revision of the data sheet is E,
and it is quite clear about this register.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This is useful as debug information since the revisions of this device
have notable differences.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
A delay of 1 ms must be added after the System Reset Command. Still wait
for ESTAT.CLKRDY afterwards as a precaution.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The Read Control Register command requires that a dummy byte be read
before the register value for the MAC and MII registers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The read/writedatabyte() functions are just a special case of
read/writedata() with a simpler API, so reuse these instead of
duplicating code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
