From fb977cb9ef77489b7c59b24495c53c5f3954db32 Mon Sep 17 00:00:00 2001 From: David Kopf Date: Tue, 15 Nov 2011 13:24:58 -0500 Subject: [PATCH] Better fix for hardware FCS error on JTAG reset Correct silly error introduced by trying to save two bytes. --- cpu/avr/radio/rf230bb/halbb.c | 8 +++++++- cpu/avr/radio/rf230bb/rf230bb.c | 19 +++++++++++++++---- platform/avr-raven/contiki-raven-main.c | 23 +++++------------------ 3 files changed, 27 insertions(+), 23 deletions(-) diff --git a/cpu/avr/radio/rf230bb/halbb.c b/cpu/avr/radio/rf230bb/halbb.c index 8e3e8f3bf..726f35e24 100644 --- a/cpu/avr/radio/rf230bb/halbb.c +++ b/cpu/avr/radio/rf230bb/halbb.c @@ -232,13 +232,19 @@ hal_init(void) // hal_reset_flags(); /*IO Specific Initialization - sleep and reset pins. */ + /* Set pins low before they are initialized as output? Does not seem to matter */ +// hal_set_rst_low(); +// hal_set_slptr_low(); DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */ DDR_RST |= (1 << RST); /* Enable RST as output. */ /*SPI Specific Initialization.*/ /* Set SS, CLK and MOSI as output. */ - HAL_DDR_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK) | (1 << HAL_DD_MOSI); + /* To avoid a SPI glitch, the port register shall be set before the DDR register */ HAL_PORT_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK); /* Set SS and CLK high */ + HAL_DDR_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK) | (1 << HAL_DD_MOSI); + HAL_DDR_SPI &=~ (1<< HAL_DD_MISO); /* MISO input */ + /* Run SPI at max speed */ SPCR = (1 << SPE) | (1 << MSTR); /* Enable SPI module and master operation. */ SPSR = (1 << SPI2X); /* Enable doubled SPI speed in master mode. */ diff --git a/cpu/avr/radio/rf230bb/rf230bb.c b/cpu/avr/radio/rf230bb/rf230bb.c index 5a63c6cb5..ea0c701b1 100644 --- a/cpu/avr/radio/rf230bb/rf230bb.c +++ b/cpu/avr/radio/rf230bb/rf230bb.c @@ -721,18 +721,29 @@ rf230_init(void) { uint8_t i; DEBUGFLOW('i'); - +/* A jtag or brownout reset of the mcu tristates the RF230 control pins while + * it is in operation, which can result in a mulfunctioning condition when the + * radio is later re-initialized. + * This manifests as an incorrectly computed hardware FCS checksum. + * Setting up the pins before the poweron time delay seems to fix this. + */ +#if 1 //this works after a brownout or jtag reset + /* Initialize Hardware Abstraction Layer */ + hal_init(); /* Wait in case VCC just applied */ delay_us(TIME_TO_ENTER_P_ON); +#else //this gives FCS errors 5 out of 6 times + /* Wait in case VCC just applied */ + delay_us(TIME_TO_ENTER_P_ON); + /* Initialize Hardware Abstraction Layer */ + hal_init(); +#endif /* Calibrate oscillator */ // printf_P(PSTR("\nBefore calibration OSCCAL=%x\n"),OSCCAL); // calibrate_rc_osc_32k(); // printf_P(PSTR("After calibration OSCCAL=%x\n"),OSCCAL); - /* Initialize Hardware Abstraction Layer */ - hal_init(); - /* Set receive buffers empty and point to the first */ for (i=0;i