split SPI code into generic and CC2420-related and renamed constants in CC2420
This commit is contained in:
joxe
parent
898c00b812
commit
f7a82a9145
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@ -28,7 +28,7 @@
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*
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*
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* This file is part of the Contiki operating system.
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* This file is part of the Contiki operating system.
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*
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*
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* @(#)$Id: cc2420.c,v 1.55 2010/06/21 19:48:00 joxe Exp $
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* @(#)$Id: cc2420.c,v 1.56 2010/06/23 10:15:28 joxe Exp $
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*/
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*/
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/*
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/*
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* This code is almost device independent and should be easy to port.
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* This code is almost device independent and should be easy to port.
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@ -150,42 +150,38 @@ static uint8_t receive_on;
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static int channel;
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static int channel;
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static uint8_t rxptr; /* Pointer to the next byte in the rxfifo. */
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static void
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static void
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getrxdata(void *buf, int len)
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getrxdata(void *buf, int len)
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{
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{
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FASTSPI_READ_FIFO_NO_WAIT(buf, len);
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SPI_READ_FIFO_BUF(buf, len);
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rxptr = (rxptr + len) & 0x7f;
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}
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}
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static void
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static void
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getrxbyte(uint8_t *byte)
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getrxbyte(uint8_t *byte)
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{
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{
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FASTSPI_READ_FIFO_BYTE(*byte);
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SPI_READ_FIFO_BYTE(*byte);
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rxptr = (rxptr + 1) & 0x7f;
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}
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}
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static void
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static void
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flushrx(void)
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flushrx(void)
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{
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{
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uint8_t dummy;
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uint8_t dummy;
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FASTSPI_READ_FIFO_BYTE(dummy);
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SPI_READ_FIFO_BYTE(dummy);
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FASTSPI_STROBE(CC2420_SFLUSHRX);
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SPI_STROBE(CC2420_SFLUSHRX);
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FASTSPI_STROBE(CC2420_SFLUSHRX);
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SPI_STROBE(CC2420_SFLUSHRX);
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rxptr = 0;
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void
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static void
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strobe(enum cc2420_register regname)
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strobe(enum cc2420_register regname)
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{
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{
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FASTSPI_STROBE(regname);
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SPI_STROBE(regname);
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static unsigned int
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static unsigned int
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status(void)
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status(void)
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{
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{
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uint8_t status;
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uint8_t status;
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FASTSPI_UPD_STATUS(status);
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SPI_GET_STATUS(status);
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return status;
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return status;
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@ -197,7 +193,7 @@ on(void)
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/* PRINTF("on\n");*/
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/* PRINTF("on\n");*/
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receive_on = 1;
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receive_on = 1;
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ENABLE_FIFOP_INT();
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CC2420_ENABLE_FIFOP_INT();
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strobe(CC2420_SRXON);
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strobe(CC2420_SRXON);
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while(!(status() & (BV(CC2420_XOSC16M_STABLE))));
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while(!(status() & (BV(CC2420_XOSC16M_STABLE))));
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ENERGEST_ON(ENERGEST_TYPE_LISTEN);
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ENERGEST_ON(ENERGEST_TYPE_LISTEN);
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@ -214,10 +210,10 @@ off(void)
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ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
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ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
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strobe(CC2420_SRFOFF);
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strobe(CC2420_SRFOFF);
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DISABLE_FIFOP_INT();
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CC2420_DISABLE_FIFOP_INT();
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LEDS_OFF(LEDS_GREEN);
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LEDS_OFF(LEDS_GREEN);
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if(!FIFOP_IS_1) {
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if(!CC2420_FIFOP_IS_1) {
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flushrx();
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flushrx();
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}
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}
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}
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}
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@ -242,14 +238,14 @@ static unsigned
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getreg(enum cc2420_register regname)
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getreg(enum cc2420_register regname)
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{
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{
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unsigned reg;
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unsigned reg;
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FASTSPI_GETREG(regname, reg);
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SPI_READ_REG(regname, reg);
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return reg;
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return reg;
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void
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static void
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setreg(enum cc2420_register regname, unsigned value)
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setreg(enum cc2420_register regname, unsigned value)
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{
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{
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FASTSPI_SETREG(regname, value);
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SPI_WRITE_REG(regname, value);
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void
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static void
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@ -276,8 +272,8 @@ cc2420_init(void)
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{
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{
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int s = splhigh();
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int s = splhigh();
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cc2420_arch_init(); /* Initalize ports and SPI. */
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cc2420_arch_init(); /* Initalize ports and SPI. */
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DISABLE_FIFOP_INT();
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CC2420_DISABLE_FIFOP_INT();
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FIFOP_INT_INIT();
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CC2420_FIFOP_INT_INIT();
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splx(s);
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splx(s);
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}
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}
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@ -377,12 +373,13 @@ cc2420_transmit(unsigned short payload_len)
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#endif /* WITH_SEND_CCA */
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#endif /* WITH_SEND_CCA */
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for(i = LOOP_20_SYMBOLS; i > 0; i--) {
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for(i = LOOP_20_SYMBOLS; i > 0; i--) {
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if(SFD_IS_1) {
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if(CC2420_SFD_IS_1) {
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if(!(status() & BV(CC2420_TX_ACTIVE))) {
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if(!(status() & BV(CC2420_TX_ACTIVE))) {
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/* SFD went high but we are not transmitting. This means that
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/* SFD went high but we are not transmitting. This means that
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we just started receiving a packet, so we drop the
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we just started receiving a packet, so we drop the
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transmission. */
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transmission. */
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RELEASE_LOCK();
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RELEASE_LOCK();
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printf("CC2420 Collission\n");
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return RADIO_TX_COLLISION;
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return RADIO_TX_COLLISION;
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}
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}
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if(receive_on) {
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if(receive_on) {
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@ -453,10 +450,10 @@ cc2420_prepare(const void *payload, unsigned short payload_len)
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checksum = crc16_data(payload, payload_len, 0);
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checksum = crc16_data(payload, payload_len, 0);
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#endif /* CC2420_CONF_CHECKSUM */
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#endif /* CC2420_CONF_CHECKSUM */
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total_len = payload_len + AUX_LEN;
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total_len = payload_len + AUX_LEN;
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FASTSPI_WRITE_FIFO(&total_len, 1);
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SPI_WRITE_FIFO_BUF(&total_len, 1);
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FASTSPI_WRITE_FIFO(payload, payload_len);
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SPI_WRITE_FIFO_BUF(payload, payload_len);
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#if CC2420_CONF_CHECKSUM
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#if CC2420_CONF_CHECKSUM
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FASTSPI_WRITE_FIFO(&checksum, CHECKSUM_LEN);
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SPI_WRITE_FIFO_BUF(&checksum, CHECKSUM_LEN);
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#endif /* CC2420_CONF_CHECKSUM */
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#endif /* CC2420_CONF_CHECKSUM */
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RELEASE_LOCK();
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RELEASE_LOCK();
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@ -574,18 +571,18 @@ cc2420_set_pan_addr(unsigned pan,
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tmp[0] = pan & 0xff;
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tmp[0] = pan & 0xff;
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tmp[1] = pan >> 8;
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tmp[1] = pan >> 8;
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FASTSPI_WRITE_RAM_LE(&tmp, CC2420RAM_PANID, 2, f);
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SPI_WRITE_RAM(&tmp, CC2420RAM_PANID, 2);
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tmp[0] = addr & 0xff;
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tmp[0] = addr & 0xff;
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tmp[1] = addr >> 8;
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tmp[1] = addr >> 8;
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FASTSPI_WRITE_RAM_LE(&tmp, CC2420RAM_SHORTADDR, 2, f);
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SPI_WRITE_RAM(&tmp, CC2420RAM_SHORTADDR, 2);
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if(ieee_addr != NULL) {
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if(ieee_addr != NULL) {
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uint8_t tmp_addr[8];
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uint8_t tmp_addr[8];
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/* LSB first, MSB last for 802.15.4 addresses in CC2420 */
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/* LSB first, MSB last for 802.15.4 addresses in CC2420 */
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for (f = 0; f < 8; f++) {
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for (f = 0; f < 8; f++) {
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tmp_addr[7 - f] = ieee_addr[f];
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tmp_addr[7 - f] = ieee_addr[f];
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}
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}
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FASTSPI_WRITE_RAM_LE(tmp_addr, CC2420RAM_IEEEADDR, 8, f);
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SPI_WRITE_RAM(tmp_addr, CC2420RAM_IEEEADDR, 8);
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}
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}
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RELEASE_LOCK();
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RELEASE_LOCK();
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}
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}
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@ -601,7 +598,7 @@ TIMETABLE_AGGREGATE(aggregate_time, 10);
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int
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int
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cc2420_interrupt(void)
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cc2420_interrupt(void)
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{
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{
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CLEAR_FIFOP_INT();
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CC2420_CLEAR_FIFOP_INT();
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process_poll(&cc2420_process);
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process_poll(&cc2420_process);
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#if CC2420_TIMETABLE_PROFILING
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#if CC2420_TIMETABLE_PROFILING
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timetable_clear(&cc2420_timetable);
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timetable_clear(&cc2420_timetable);
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@ -609,7 +606,6 @@ cc2420_interrupt(void)
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#endif /* CC2420_TIMETABLE_PROFILING */
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#endif /* CC2420_TIMETABLE_PROFILING */
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pending++;
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pending++;
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cc2420_packets_seen++;
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cc2420_packets_seen++;
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return 1;
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return 1;
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}
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}
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@ -656,7 +652,7 @@ cc2420_read(void *buf, unsigned short bufsize)
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uint16_t checksum;
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uint16_t checksum;
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#endif /* CC2420_CONF_CHECKSUM */
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#endif /* CC2420_CONF_CHECKSUM */
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if(!FIFOP_IS_1) {
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if(!CC2420_FIFOP_IS_1) {
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return 0;
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return 0;
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}
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}
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/* if(!pending) {
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/* if(!pending) {
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@ -724,8 +720,8 @@ cc2420_read(void *buf, unsigned short bufsize)
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len = AUX_LEN;
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len = AUX_LEN;
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}
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}
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if(FIFOP_IS_1) {
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if(CC2420_FIFOP_IS_1) {
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if(!FIFO_IS_1) {
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if(!CC2420_FIFO_IS_1) {
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/* Clean up in case of FIFO overflow! This happens for every
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/* Clean up in case of FIFO overflow! This happens for every
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* full length frame and is signaled by FIFOP = 1 and FIFO =
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* full length frame and is signaled by FIFOP = 1 and FIFO =
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* 0. */
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* 0. */
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@ -831,7 +827,7 @@ cc2420_cca(void)
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/* printf("cc2420_rssi: RSSI not valid.\n"); */
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/* printf("cc2420_rssi: RSSI not valid.\n"); */
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}
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}
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cca = CCA_IS_1;
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cca = CC2420_CCA_IS_1;
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if(radio_was_off) {
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if(radio_was_off) {
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cc2420_off();
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cc2420_off();
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@ -843,13 +839,13 @@ cc2420_cca(void)
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int
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int
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cc2420_receiving_packet(void)
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cc2420_receiving_packet(void)
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{
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{
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return SFD_IS_1;
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return CC2420_SFD_IS_1;
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static int
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static int
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pending_packet(void)
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pending_packet(void)
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{
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{
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return FIFOP_IS_1;
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return CC2420_FIFOP_IS_1;
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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void
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void
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@ -28,7 +28,7 @@
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*
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*
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* This file is part of the Contiki operating system.
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* This file is part of the Contiki operating system.
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*
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*
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* $Id: cc2420.h,v 1.9 2010/02/23 18:24:49 adamdunkels Exp $
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* $Id: cc2420.h,v 1.10 2010/06/23 10:15:28 joxe Exp $
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*/
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*/
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/**
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/**
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@ -36,13 +36,16 @@
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* CC2420 driver header file
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* CC2420 driver header file
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* \author
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* \author
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* Adam Dunkels <adam@sics.se>
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* Adam Dunkels <adam@sics.se>
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* Joakim Eriksson <joakime@sics.se>
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*/
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*/
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#ifndef __CC2420_H__
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#ifndef __CC2420_H__
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#define __CC2420_H__
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#define __CC2420_H__
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#include "contiki.h"
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#include "contiki.h"
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#include "spi.h"
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#include "dev/radio.h"
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#include "dev/radio.h"
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#include "cc2420_const.h"
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int cc2420_init(void);
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int cc2420_init(void);
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@ -86,4 +89,102 @@ int cc2420_off(void);
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void cc2420_set_cca_threshold(int value);
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void cc2420_set_cca_threshold(int value);
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/************************************************************************/
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/* Additional SPI Macros for the CC2420 */
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/************************************************************************/
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/* Send a strobe to the CC2420 */
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#define SPI_STROBE(s) \
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do { \
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CC2420_SPI_ENABLE(); \
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SPI_WRITE(s); \
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CC2420_SPI_DISABLE(); \
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} while (0)
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/* Write to a register in the CC2420 */
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/* Note: the SPI_WRITE(0) seems to be needed for getting the */
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/* write reg working on the Z1 / MSP430X platform */
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#define SPI_WRITE_REG(adr,data) \
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do { \
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CC2420_SPI_ENABLE(); \
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SPI_WRITE_FAST(adr); \
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SPI_WRITE_FAST((uint8_t)((data) >> 8)); \
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SPI_WRITE_FAST((uint8_t)(data & 0xff)); \
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SPI_WAITFORTx_ENDED(); \
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SPI_WRITE(0); \
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CC2420_SPI_DISABLE(); \
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} while(0)
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/* Read a register in the CC2420 */
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#define SPI_READ_REG(adr,data) \
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do { \
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CC2420_SPI_ENABLE(); \
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SPI_WRITE(adr | 0x40); \
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data = (uint8_t)SPI_RXBUF; \
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SPI_TXBUF = 0; \
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SPI_WAITFOREORx(); \
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data = SPI_RXBUF << 8; \
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SPI_TXBUF = 0; \
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SPI_WAITFOREORx(); \
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data |= SPI_RXBUF; \
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CC2420_SPI_DISABLE(); \
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} while(0)
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#define SPI_READ_FIFO_BYTE(data) \
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do { \
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CC2420_SPI_ENABLE(); \
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SPI_WRITE(CC2420_RXFIFO | 0x40); \
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(void)SPI_RXBUF; \
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SPI_READ(data); \
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clock_delay(1); \
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CC2420_SPI_DISABLE(); \
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} while(0)
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#define SPI_READ_FIFO_BUF(buffer,count) \
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do { \
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uint8_t i; \
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CC2420_SPI_ENABLE(); \
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SPI_WRITE(CC2420_RXFIFO | 0x40); \
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(void)SPI_RXBUF; \
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for(i = 0; i < (count); i++) { \
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SPI_READ(((uint8_t *)(buffer))[i]); \
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} \
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clock_delay(1); \
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CC2420_SPI_DISABLE(); \
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} while(0)
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#define SPI_WRITE_FIFO_BUF(buffer,count) \
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do { \
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uint8_t i; \
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CC2420_SPI_ENABLE(); \
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SPI_WRITE_FAST(CC2420_TXFIFO); \
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for(i = 0; i < (count); i++) { \
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SPI_WRITE_FAST(((uint8_t *)(buffer))[i]); \
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} \
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SPI_WAITFORTx_ENDED(); \
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CC2420_SPI_DISABLE(); \
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} while(0)
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/* Write to RAM in the CC2420 */
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#define SPI_WRITE_RAM(buffer,adr,count) \
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do { \
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uint8_t i; \
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CC2420_SPI_ENABLE(); \
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SPI_WRITE_FAST(0x80 | (adr & 0x7f)); \
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||||||
|
SPI_WRITE_FAST((adr >> 1) & 0xc0); \
|
||||||
|
for(i = 0; i < (count); i++) { \
|
||||||
|
SPI_WRITE_FAST(((uint8_t*)(buffer))[i]); \
|
||||||
|
} \
|
||||||
|
SPI_WAITFORTx_ENDED(); \
|
||||||
|
CC2420_SPI_DISABLE(); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
/* Read status of the CC2420 */
|
||||||
|
#define SPI_GET_STATUS(s) \
|
||||||
|
do { \
|
||||||
|
CC2420_SPI_ENABLE(); \
|
||||||
|
SPI_WRITE(CC2420_SNOP); \
|
||||||
|
s = SPI_RXBUF; \
|
||||||
|
CC2420_SPI_DISABLE(); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
#endif /* __CC2420_H__ */
|
#endif /* __CC2420_H__ */
|
||||||
|
|
|
||||||
306
core/dev/spi.h
306
core/dev/spi.h
|
|
@ -1,8 +1,44 @@
|
||||||
/* -*- C -*- */
|
/*
|
||||||
/* @(#)$Id: spi.h,v 1.7 2010/03/15 23:01:37 nifi Exp $ */
|
* Copyright (c) 2010, Swedish Institute of Computer Science.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of the Institute nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* $Id: spi.h,v 1.8 2010/06/23 10:15:28 joxe Exp $
|
||||||
|
*/
|
||||||
|
|
||||||
#ifndef SPI_H
|
/**
|
||||||
#define SPI_H
|
* \file
|
||||||
|
* Basic SPI macros
|
||||||
|
* \author
|
||||||
|
* Joakim Eriksson <joakime@sics.se>
|
||||||
|
* Niclas Finne <nfi@sics.se>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __SPI_H__
|
||||||
|
#define __SPI_H__
|
||||||
|
|
||||||
/* Define macros to use for checking SPI transmission status depending
|
/* Define macros to use for checking SPI transmission status depending
|
||||||
on if it is possible to wait for TX buffer ready. This is possible
|
on if it is possible to wait for TX buffer ready. This is possible
|
||||||
|
|
@ -21,238 +57,36 @@ extern unsigned char spi_busy;
|
||||||
|
|
||||||
void spi_init(void);
|
void spi_init(void);
|
||||||
|
|
||||||
/******************************************************************************************************
|
/* Write one character to SPI */
|
||||||
* TEXAS INSTRUMENTS INC., *
|
#define SPI_WRITE(data) \
|
||||||
* MSP430 APPLICATIONS. *
|
|
||||||
* Copyright Texas Instruments Inc, 2004 *
|
|
||||||
*****************************************************************************************************/
|
|
||||||
|
|
||||||
/***********************************************************
|
|
||||||
FAST SPI: Low level functions
|
|
||||||
***********************************************************/
|
|
||||||
|
|
||||||
#define FASTSPI_TX(x)\
|
|
||||||
do {\
|
|
||||||
SPI_WAITFORTx_BEFORE();\
|
|
||||||
SPI_TXBUF = x;\
|
|
||||||
SPI_WAITFORTx_AFTER();\
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
#define FASTSPI_RX(x)\
|
|
||||||
do {\
|
|
||||||
SPI_TXBUF = 0;\
|
|
||||||
SPI_WAITFOREORx();\
|
|
||||||
x = SPI_RXBUF;\
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
#define FASTSPI_CLEAR_RX(x) do{ SPI_RXBUF; }while(0)
|
|
||||||
|
|
||||||
#define FASTSPI_RX_GARBAGE()\
|
|
||||||
do {\
|
|
||||||
SPI_TXBUF = 0;\
|
|
||||||
SPI_WAITFOREORx();\
|
|
||||||
(void)SPI_RXBUF;\
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
#define FASTSPI_TX_MANY(p,c)\
|
|
||||||
do {\
|
|
||||||
u8_t spiCnt;\
|
|
||||||
for (spiCnt = 0; spiCnt < (c); spiCnt++) {\
|
|
||||||
FASTSPI_TX(((u8_t*)(p))[spiCnt]);\
|
|
||||||
}\
|
|
||||||
SPI_WAITFORTx_ENDED();\
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
|
|
||||||
#define FASTSPI_RX_WORD(x)\
|
|
||||||
do {\
|
|
||||||
SPI_TXBUF = 0;\
|
|
||||||
SPI_WAITFOREORx();\
|
|
||||||
x = SPI_RXBUF << 8;\
|
|
||||||
SPI_TXBUF = 0;\
|
|
||||||
SPI_WAITFOREORx();\
|
|
||||||
x |= SPI_RXBUF;\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define FASTSPI_TX_ADDR(a)\
|
|
||||||
do {\
|
|
||||||
SPI_TXBUF = a;\
|
|
||||||
SPI_WAITFOREOTx();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define FASTSPI_RX_ADDR(a)\
|
|
||||||
do {\
|
|
||||||
SPI_TXBUF = (a) | 0x40;\
|
|
||||||
SPI_WAITFOREOTx();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/***********************************************************
|
|
||||||
FAST SPI: Register access
|
|
||||||
***********************************************************/
|
|
||||||
// s = command strobe
|
|
||||||
// a = register address
|
|
||||||
// v = register value
|
|
||||||
|
|
||||||
#define FASTSPI_STROBE(s) \
|
|
||||||
do {\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
FASTSPI_TX_ADDR(s);\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define FASTSPI_SETREG(a,v)\
|
|
||||||
do {\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
FASTSPI_TX_ADDR(a);\
|
|
||||||
FASTSPI_TX((u8_t) ((v) >> 8));\
|
|
||||||
FASTSPI_TX((u8_t) (v));\
|
|
||||||
SPI_WAITFORTx_ENDED();\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
|
|
||||||
#define FASTSPI_GETREG(a,v)\
|
|
||||||
do {\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
FASTSPI_RX_ADDR(a);\
|
|
||||||
v= (u8_t)SPI_RXBUF;\
|
|
||||||
FASTSPI_RX_WORD(v);\
|
|
||||||
clock_delay(1);\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
// Updates the SPI status byte
|
|
||||||
|
|
||||||
#define FASTSPI_UPD_STATUS(s)\
|
|
||||||
do {\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
SPI_TXBUF = CC2420_SNOP;\
|
|
||||||
SPI_WAITFOREOTx();\
|
|
||||||
s = SPI_RXBUF;\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/***********************************************************
|
|
||||||
FAST SPI: FIFO Access
|
|
||||||
***********************************************************/
|
|
||||||
// p = pointer to the byte array to be read/written
|
|
||||||
// c = the number of bytes to read/write
|
|
||||||
// b = single data byte
|
|
||||||
|
|
||||||
#define FASTSPI_WRITE_FIFO(p,c)\
|
|
||||||
do {\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
u8_t i;\
|
|
||||||
FASTSPI_TX_ADDR(CC2420_TXFIFO);\
|
|
||||||
for (i = 0; i < (c); i++) {\
|
|
||||||
FASTSPI_TX(((u8_t*)(p))[i]);\
|
|
||||||
}\
|
|
||||||
SPI_WAITFORTx_ENDED();\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define FASTSPI_WRITE_FIFO_NOCE(p,c)\
|
|
||||||
do {\
|
|
||||||
FASTSPI_TX_ADDR(CC2420_TXFIFO);\
|
|
||||||
for (u8_t spiCnt = 0; spiCnt < (c); spiCnt++) {\
|
|
||||||
FASTSPI_TX(((u8_t*)(p))[spiCnt]);\
|
|
||||||
}\
|
|
||||||
SPI_WAITFORTx_ENDED();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define FASTSPI_READ_FIFO_BYTE(b)\
|
|
||||||
do {\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
FASTSPI_RX_ADDR(CC2420_RXFIFO);\
|
|
||||||
(void)SPI_RXBUF;\
|
|
||||||
FASTSPI_RX(b);\
|
|
||||||
clock_delay(1);\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
|
|
||||||
#define FASTSPI_READ_FIFO_NO_WAIT(p,c)\
|
|
||||||
do {\
|
|
||||||
u8_t spiCnt;\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
FASTSPI_RX_ADDR(CC2420_RXFIFO);\
|
|
||||||
(void)SPI_RXBUF;\
|
|
||||||
for (spiCnt = 0; spiCnt < (c); spiCnt++) {\
|
|
||||||
FASTSPI_RX(((u8_t*)(p))[spiCnt]);\
|
|
||||||
}\
|
|
||||||
clock_delay(1);\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#define FASTSPI_READ_FIFO_GARBAGE(c)\
|
|
||||||
do {\
|
|
||||||
u8_t spiCnt;\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
FASTSPI_RX_ADDR(CC2420_RXFIFO);\
|
|
||||||
(void)SPI_RXBUF;\
|
|
||||||
for (spiCnt = 0; spiCnt < (c); spiCnt++) {\
|
|
||||||
FASTSPI_RX_GARBAGE();\
|
|
||||||
}\
|
|
||||||
clock_delay(1);\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/***********************************************************
|
|
||||||
FAST SPI: CC2420 RAM access (big or little-endian order)
|
|
||||||
***********************************************************/
|
|
||||||
// FAST SPI: CC2420 RAM access (big or little-endian order)
|
|
||||||
// p = pointer to the variable to be written
|
|
||||||
// a = the CC2420 RAM address
|
|
||||||
// c = the number of bytes to write
|
|
||||||
// n = counter variable which is used in for/while loops (u8_t)
|
|
||||||
//
|
|
||||||
// Example of usage:
|
|
||||||
// u8_t n;
|
|
||||||
// u16_t shortAddress = 0xBEEF;
|
|
||||||
// FASTSPI_WRITE_RAM_LE(&shortAddress, CC2420RAM_SHORTADDR, 2);
|
|
||||||
|
|
||||||
|
|
||||||
#define FASTSPI_WRITE_RAM_LE(p,a,c,n)\
|
|
||||||
do {\
|
|
||||||
SPI_ENABLE();\
|
|
||||||
FASTSPI_TX(0x80 | (a & 0x7F));\
|
|
||||||
FASTSPI_TX((a >> 1) & 0xC0);\
|
|
||||||
for (n = 0; n < (c); n++) {\
|
|
||||||
FASTSPI_TX(((u8_t*)(p))[n]);\
|
|
||||||
}\
|
|
||||||
SPI_WAITFORTx_ENDED();\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define FASTSPI_WRITE_RAM_BE(p,a,c,n) \
|
|
||||||
do { \
|
do { \
|
||||||
SPI_ENABLE(); \
|
SPI_WAITFORTx_BEFORE(); \
|
||||||
FASTSPI_TX(0x80 | (a & 0x7F)); \
|
SPI_TXBUF = data; \
|
||||||
FASTSPI_TX((a >> 1) & 0xC0); \
|
SPI_WAITFOREOTx(); \
|
||||||
for (n = (c); n > 0; n--) { \
|
} while(0)
|
||||||
FASTSPI_TX(((uint8_t *)(p))[n - 1]); \
|
|
||||||
} \
|
|
||||||
SPI_WAITFORTx_ENDED(); \
|
|
||||||
SPI_DISABLE(); \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define FASTSPI_READ_RAM_LE(p,a,c,n)\
|
/* Write one character to SPI - will not wait for end
|
||||||
do {\
|
useful for multiple writes with wait after final */
|
||||||
SPI_ENABLE();\
|
#define SPI_WRITE_FAST(data) \
|
||||||
FASTSPI_TX(0x80 | (a & 0x7F));\
|
do { \
|
||||||
FASTSPI_TX(((a >> 1) & 0xC0) | 0x20);\
|
SPI_WAITFORTx_BEFORE(); \
|
||||||
SPI_WAITFORTx_ENDED();\
|
SPI_TXBUF = data; \
|
||||||
SPI_RXBUF;\
|
SPI_WAITFORTx_AFTER(); \
|
||||||
for (n = 0; n < (c); n++) {\
|
} while(0)
|
||||||
FASTSPI_RX(((u8_t*)(p))[n]);\
|
|
||||||
}\
|
|
||||||
SPI_DISABLE();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#endif /* SPI_H */
|
/* Read one character from SPI */
|
||||||
|
#define SPI_READ(data) \
|
||||||
|
do { \
|
||||||
|
SPI_TXBUF = 0; \
|
||||||
|
SPI_WAITFOREORx(); \
|
||||||
|
data = SPI_RXBUF; \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
/* Flush the SPI read register */
|
||||||
|
#define SPI_FLUSH() \
|
||||||
|
do { \
|
||||||
|
SPI_RXBUF; \
|
||||||
|
} while(0);
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __SPI_H__ */
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue