MSP430 setup for f2xxx based on Z1
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Niclas Finne
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f3db12c19d
1 changed files with 45 additions and 80 deletions
333
cpu/msp430/f2xxx/msp430.c
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333
cpu/msp430/f2xxx/msp430.c
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/*
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* Copyright (c) 2005, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*/
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#include "contiki.h"
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#include "dev/watchdog.h"
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#if defined(__MSP430__) && defined(__GNUC__)
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#define asmv(arg) __asm__ __volatile__(arg)
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#endif
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/*---------------------------------------------------------------------------*/
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#if defined(__MSP430__) && defined(__GNUC__) && MSP430_MEMCPY_WORKAROUND
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void *
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w_memcpy(void *out, const void *in, size_t n)
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{
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uint8_t *src, *dest;
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src = (uint8_t *) in;
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dest = (uint8_t *) out;
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while(n-- > 0) {
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*dest++ = *src++;
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}
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return out;
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}
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#endif /* __GNUC__ && __MSP430__ && MSP430_MEMCPY_WORKAROUND */
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/*---------------------------------------------------------------------------*/
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#if defined(__MSP430__) && defined(__GNUC__) && MSP430_MEMCPY_WORKAROUND
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void *
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w_memset(void *out, int value, size_t n)
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{
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uint8_t *dest;
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dest = (uint8_t *) out;
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while(n-- > 0) {
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*dest++ = value & 0xff;
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}
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return out;
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}
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#endif /* __GNUC__ && __MSP430__ && MSP430_MEMCPY_WORKAROUND */
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/*---------------------------------------------------------------------------*/
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void
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msp430_init_dco(void)
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{
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if(CALBC1_8MHZ != 0xFF) {
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DCOCTL = 0x00;
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BCSCTL1 = CALBC1_8MHZ; /*Set DCO to 8MHz */
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DCOCTL = CALDCO_8MHZ;
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} else { /*start using reasonable values at 8 Mhz */
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DCOCTL = 0x00;
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BCSCTL1 = 0x8D;
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DCOCTL = 0x88;
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}
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/*BCSCTL1 |= XT2OFF; // Make sure XT2 is off */
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/* BCSCTL2 = 0x00; // MCLK = DCOCLK/1 */
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/* SMCLK = DCOCLK/1 */
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/* DCO Internal Resistor */
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Start CPU with full speed (? good or bad?) and go downwards */
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/*---------------------------------------------------------------------------*/
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void
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msp430_quick_synch_dco(void) {
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uint16_t last;
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uint16_t diff;
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uint16_t dco_reg = 0x0fff;
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uint8_t current_bit = 12;
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uint16_t i;
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/* DELTA_2 assumes an ACLK of 32768 Hz */
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#define DELTA_2 ((MSP430_CPU_SPEED) / 32768)
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/* Select SMCLK clock, and capture on ACLK for TBCCR6 */
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TBCTL = TBSSEL1 | TBCLR;
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TBCCTL6 = CCIS0 + CM0 + CAP;
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/* start the timer */
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TBCTL |= MC1;
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BCSCTL1 = 0x8D | 7;
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DCOCTL = 0xff; /* MAX SPEED ?? */
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/* IDEA: do binary search - check MSB first, etc... */
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/* 1 set current bit to zero - if to slow, put back to 1 */
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while(current_bit--) {
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/* first set the current bit to zero and check - we know that it is
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set from start so ^ works (first bit = bit 11) */
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dco_reg = dco_reg ^ (1 << current_bit); /* clear bit 11..10..9.. */
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/* set dco registers */
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DCOCTL = dco_reg & 0xff;
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BCSCTL1 = (BCSCTL1 & 0xf8) | (dco_reg >> 8);
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/* some delay to make clock stable - could possibly be made using
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captures too ... */
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for(i=0; i < 1000; i++) {
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i = i | 1;
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}
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/* do capture... */
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while(!(TBCCTL6 & CCIFG));
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last = TBCCR6;
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TBCCTL6 &= ~CCIFG;
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/* wait for next Capture - and calculate difference */
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while(!(TBCCTL6 & CCIFG));
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diff = TBCCR6 - last;
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/* /\* store what was run during the specific test *\/ */
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/* dcos[current_bit] = dco_reg; */
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/* vals[current_bit] = diff; */
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/* should we keep the bit cleared or not ? */
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if(diff < DELTA_2) { /* DCO is too slow - fewer ticks than desired */
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/* toggle bit again to get it back to one */
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dco_reg = dco_reg ^ (1 << current_bit);
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}
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}
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}
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/*---------------------------------------------------------------------------*/
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static void
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init_ports(void)
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{
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/* Turn everything off, device drivers enable what is needed. */
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/* All configured for digital I/O */
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#ifdef P1SEL
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P1SEL = 0;
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#endif
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#ifdef P2SEL
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P2SEL = 0;
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#endif
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#ifdef P3SEL
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P3SEL = 0;
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#endif
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#ifdef P4SEL
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P4SEL = 0;
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#endif
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#ifdef P5SEL
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P5SEL = 0;
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#endif
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#ifdef P6SEL
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P6SEL = 0;
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#endif
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/* All available inputs */
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#ifdef P1DIR
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P1DIR = 0;
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P1OUT = 0;
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#endif
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#ifdef P2DIR
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P2DIR = 0;
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P2OUT = 0;
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#endif
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#ifdef P3DIR
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P3DIR = 0;
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P3OUT = 0;
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#endif
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#ifdef P4DIR
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P4DIR = 0;
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P4OUT = 0;
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#endif
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#ifdef P5DIR
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P5DIR = 0;
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P5OUT = 0;
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#endif
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#ifdef P6DIR
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P6DIR = 0;
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P6OUT = 0;
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#endif
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#ifdef P7DIR
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P7DIR = 0;
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P7OUT = 0;
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#endif
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#ifdef P8DIR
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P8DIR = 0;
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P8OUT = 0;
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#endif
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P1IE = 0;
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P2IE = 0;
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}
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/*---------------------------------------------------------------------------*/
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/* msp430-ld may align _end incorrectly. Workaround in cpu_init. */
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#if defined(__MSP430__) && defined(__GNUC__)
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extern int _end; /* Not in sys/unistd.h */
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static char *cur_break = (char *)&_end;
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#endif
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void
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msp430_cpu_init(void)
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{
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dint();
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watchdog_init();
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init_ports();
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msp430_quick_synch_dco();
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eint();
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#if defined(__MSP430__) && defined(__GNUC__)
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if((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug! */
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cur_break++;
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}
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#endif
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*
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* Mask all interrupts that can be masked.
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*/
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int
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splhigh_(void)
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{
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/* Clear the GIE (General Interrupt Enable) flag. */
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int sr;
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#ifdef __IAR_SYSTEMS_ICC__
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sr = __get_SR_register();
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__bic_SR_register(GIE);
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#else
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asmv("mov r2, %0" : "=r" (sr));
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asmv("bic %0, r2" : : "i" (GIE));
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#endif
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return sr & GIE; /* Ignore other sr bits. */
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Restore previous interrupt mask.
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*/
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/* void */
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/* splx_(int sr) */
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/* { */
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/* #ifdef __IAR_SYSTEMS_ICC__ */
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/* __bis_SR_register(sr); */
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/* #else */
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/* /\* If GIE was set, restore it. *\/ */
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/* asmv("bis %0, r2" : : "r" (sr)); */
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/* #endif */
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/* } */
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/*---------------------------------------------------------------------------*/
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#ifdef __IAR_SYSTEMS_ICC__
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int __low_level_init(void)
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{
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/* turn off watchdog so that C-init will run */
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WDTCTL = WDTPW + WDTHOLD;
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/*
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* Return value:
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*
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* 1 - Perform data segment initialization.
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* 0 - Skip data segment initialization.
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*/
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return 1;
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}
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#endif
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/*---------------------------------------------------------------------------*/
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#if DCOSYNCH_CONF_ENABLED
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/* this code will always start the TimerB if not already started */
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void
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msp430_sync_dco(void) {
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uint16_t last;
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uint16_t diff;
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/* uint32_t speed; */
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/* DELTA_2 assumes an ACLK of 32768 Hz */
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#define DELTA_2 ((MSP430_CPU_SPEED) / 32768)
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/* Select SMCLK clock, and capture on ACLK for TBCCR6 */
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TBCTL = TBSSEL1 | TBCLR;
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TBCCTL6 = CCIS0 + CM0 + CAP;
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/* start the timer */
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TBCTL |= MC1;
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/* wait for next Capture */
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TBCCTL6 &= ~CCIFG;
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while(!(TBCCTL6 & CCIFG));
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last = TBCCR6;
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TBCCTL6 &= ~CCIFG;
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/* wait for next Capture - and calculate difference */
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while(!(TBCCTL6 & CCIFG));
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diff = TBCCR6 - last;
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/* Stop timer - conserves energy according to user guide */
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TBCTL = 0;
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/* speed = diff; */
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/* speed = speed * 32768; */
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/* printf("Last TAR diff:%d target: %ld ", diff, DELTA_2); */
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/* printf("CPU Speed: %lu DCOCTL: %d\n", speed, DCOCTL); */
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/* resynchronize the DCO speed if not at target */
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if(DELTA_2 < diff) { /* DCO is too fast, slow it down */
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DCOCTL--;
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if(DCOCTL == 0xFF) { /* Did DCO role under? */
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BCSCTL1--;
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}
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} else if(DELTA_2 > diff) {
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DCOCTL++;
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if(DCOCTL == 0x00) { /* Did DCO role over? */
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BCSCTL1++;
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}
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}
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}
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#endif /* DCOSYNCH_CONF_ENABLED */
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/*---------------------------------------------------------------------------*/
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