Add combined MCU and radio ATmega128rfa1
This commit is contained in:
dak664
parent
ee65d0d887
commit
f1f32c8e6a
9 changed files with 609 additions and 114 deletions
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@ -42,8 +42,14 @@
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#if defined(__AVR__)
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#include <avr/io.h>
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#include <util/delay.h>
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#define delay_us( us ) ( _delay_us( ( us ) ) )
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//_delay_us has the potential to use floating point which brings the 256 byte clz table into RAM
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//#include <util/delay.h>
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//#define delay_us( us ) ( _delay_us( ( us ) ) )
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//_delay_loop_2(uint16_t count) is 4 CPU cycles per iteration, up to 32 milliseconds at 8MHz
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#include <util/delay_basic.h>
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#define delay_us( us ) ( _delay_loop_2(1+(us*F_CPU)/4000000UL) )
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#include <avr/pgmspace.h>
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#elif defined(__MSP430__)
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#include <io.h>
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@ -116,6 +122,7 @@ struct timestamp {
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#define RADIOSLEEPSWHENOFF 1
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#endif
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//RS232 delays will cause 6lowpan fragment overruns!
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#define DEBUG 0
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#if DEBUG
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#define PRINTF(FORMAT,args...) printf_P(PSTR(FORMAT),##args)
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@ -141,6 +148,9 @@ struct timestamp {
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#if RADIOSTATS
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uint16_t RF230_sendpackets,RF230_receivepackets,RF230_sendfail,RF230_receivefail;
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#endif
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/* Set in clock.c every 256 seconds */
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uint8_t rf230_calibrate;
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uint8_t rf230_calibrated; //debugging
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/* Track flow through driver, see contiki-raven-main.c for example of use */
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//#define DEBUGFLOWSIZE 64
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@ -217,7 +227,8 @@ uint8_t RF230_receive_on,RF230_sleeping;
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static uint8_t channel;
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/* Received frames are buffered to rxframe in the interrupt routine in hal.c */
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hal_rx_frame_t rxframe;
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uint8_t rxframe_head,rxframe_tail;
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hal_rx_frame_t rxframe[RF230_CONF_RX_BUFFERS];
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/*----------------------------------------------------------------------------*/
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/** \brief This function return the Radio Transceivers current state.
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@ -450,7 +461,7 @@ rf230_is_ready_to_send() {
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static void
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flushrx(void)
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{
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rxframe.length=0;
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rxframe[rxframe_head].length=0;
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t locked, lock_on, lock_off;
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@ -538,32 +549,148 @@ set_txpower(uint8_t power)
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hal_subregister_write(SR_TX_PWR, power);
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}
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}
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/*----------------------------------------------------------------------------*/
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/**
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\brief Calibrate the internal RC oscillator
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This function calibrates the internal RC oscillator, based
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on an external 32KHz crystal connected to TIMER2. In order to
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verify the calibration result you can program the CKOUT fuse
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and monitor the CPU clock on an I/O pin.
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*/
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#define AVR_ENTER_CRITICAL_REGION( ) {uint8_t volatile saved_sreg = SREG; cli( )
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#define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;}
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uint8_t osccal_original,osccal_calibrated;
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void
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calibrate_rc_osc_32k(void)
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{
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#if 1
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/* Calibrate RC Oscillator: The calibration routine is done by clocking TIMER2
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* from the external 32kHz crystal while running an internal timer simultaneously.
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* The internal timer will be clocked at the same speed as the internal RC
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* oscillator, while TIMER2 is running at 32768 Hz. This way it is not necessary
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* to use a timed loop, and keep track cycles in timed loop vs. optimization
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* and compiler.
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*/
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uint8_t osccal_original = OSCCAL;
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volatile uint16_t temp;
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/* Start with current value, which for some MCUs could be in upper or lower range */
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// PRR0 &= ~((1 << PRTIM2)|(1 << PRTIM1)); /* Enable Timer 1 and 2 */
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TIMSK2 = 0x00; /* Disable Timer/Counter 2 interrupts. */
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TIMSK1 = 0x00; /* Disable Timer/Counter 1 interrupts. */
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/* Enable TIMER/COUNTER 2 to be clocked from the external 32kHz clock crystal.
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* Then wait for the timer to become stable before doing any calibration.
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*/
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ASSR |= (1 << AS2);
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// while (ASSR & ((1 << TCN2UB)|(1 << OCR2AUB)|(1 << TCR2AUB)|(1 << TCR2BUB))) { ; }
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TCCR2B = 1 << CS20; /* run timer 2 at divide by 1 (32KHz) */
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delay_us(50000UL); //crystal takes significant time to stabilize
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AVR_ENTER_CRITICAL_REGION();
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uint8_t counter = 128;
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bool cal_ok = false;
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do{
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/* wait for timer to be ready for updated config */
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TCCR1B = 1 << CS10;
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while (ASSR & ((1 << TCN2UB)|(1 << OCR2AUB)|(1 << TCR2AUB)|(1 << TCR2BUB))) { ; }
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TCNT2 = 0x80;
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TCNT1 = 0;
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TIFR2 = 0xFF; /* Clear TIFR2 flags (Yes, really) */
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/* Wait for TIMER/COUNTER 2 to overflow. Stop TIMER/COUNTER 1 and 2, and
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* read the counter value of TIMER/COUNTER 1. It will now contain the
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* number of cpu cycles elapsed within the 3906.25 microsecond period.
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*/
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while (!(TIFR2 & (1 << TOV2))){
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;
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}
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temp = TCNT1;
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TCCR1B = 0;
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/* Defining these as floating point introduces a lot of code and the 256 byte .clz table to RAM */
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/* At 8 MHz we would expect 8*3906.25 = 31250 CPU clocks */
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#define cal_upper 32812 //(31250*1.05) // 32812 = 0x802c
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#define cal_lower 29687 //(31250*0.95) // 29687 = 0x73f7
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/* Iteratively reduce the error to be within limits */
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if (temp < cal_lower) {
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/* Too slow. Put the hammer down. */
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if (OSCCAL==0x7e) break; //stay in lowest range
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if (OSCCAL==0xff) break;
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OSCCAL++;
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} else if (temp > cal_upper) {
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/* Too fast, retard. */
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if (OSCCAL==0x81) break; //stay in highest range
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if (OSCCAL==0x00) break;
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OSCCAL--;
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} else {
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/* The CPU clock frequency is now within +/- 0.5% of the target value. */
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cal_ok = true;
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}
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counter--;
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} while ((counter != 0) && (false == cal_ok));
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osccal_calibrated=OSCCAL;
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if (true != cal_ok) {
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/* We failed, therefore restore previous OSCCAL value. */
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OSCCAL = osccal_original;
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}
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OSCCAL = osccal_original;
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TCCR2B = 0;
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ASSR &= ~(1 << AS2);
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/* Disable both timers again to save power. */
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// PRR0 |= (1 << PRTIM2);/* |(1 << PRTIM1); */
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AVR_LEAVE_CRITICAL_REGION();
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#endif
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}
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/*---------------------------------------------------------------------------*/
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int
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rf230_init(void)
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{
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uint8_t i;
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DEBUGFLOW('I');
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/* Wait in case VCC just applied */
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/* Wait in case VCC just applied */
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delay_us(TIME_TO_ENTER_P_ON);
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/* Calibrate oscillator */
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// calibrate_rc_osc_32k();
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// printf_P(PSTR("\nBefore calibration OSCCAL=%x\n"),OSCCAL);
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// calibrate_rc_osc_32k();
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// printf_P(PSTR("After calibration OSCCAL=%x\n"),OSCCAL);
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/* Initialize Hardware Abstraction Layer. */
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/* Initialize Hardware Abstraction Layer */
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hal_init();
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/* Set receive buffers empty and point to the first */
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for (i=0;i<RF230_CONF_RX_BUFFERS;i++) rxframe[i].length=0;
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rxframe_head=0;rxframe_tail=0;
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/* Do full rf230 Reset */
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hal_set_rst_low();
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hal_set_slptr_low();
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delay_us(TIME_RESET);
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hal_set_rst_high();
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/* Force transition to TRX_OFF. */
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/* Force transition to TRX_OFF */
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hal_subregister_write(SR_TRX_CMD, CMD_FORCE_TRX_OFF);
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delay_us(TIME_P_ON_TO_TRX_OFF);
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/* Verify that it is a supported version */
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/* Note gcc optimizes this away if DEBUG is not set! */
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//ATMEGA128RFA1 - version 4, ID 31
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uint8_t tvers = hal_register_read(RG_VERSION_NUM);
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uint8_t tmanu = hal_register_read(RG_MAN_ID_0);
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@ -577,6 +704,12 @@ rf230_init(void)
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/* Set up number of automatic retries 0-15 (0 implies PLL_ON sends instead of the extended TX_ARET mode */
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hal_subregister_write(SR_MAX_FRAME_RETRIES, RF230_CONF_AUTORETRIES );
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/* Set up carrier sense/clear channel assesment parameters for extended operating mode */
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hal_subregister_write(SR_MAX_CSMA_RETRIES, 5 );//highest allowed retries
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hal_register_write(RG_CSMA_BE, 0x80); //min backoff exponent 0, max 8 (highest allowed)
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hal_register_write(RG_CSMA_SEED_0,hal_register_read(RG_PHY_RSSI) );//upper two RSSI reg bits RND_VALUE are random in rf231
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// hal_register_write(CSMA_SEED_1,42 );
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/* Use automatic CRC unless manual is specified */
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#if RF230_CONF_CHECKSUM
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@ -619,10 +752,20 @@ rf230_transmit(unsigned short payload_len)
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radiowason=RF230_receive_on;
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/* If radio is sleeping we have to turn it on first */
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/* This automatically does the PLL calibrations */
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if (RF230_sleeping) {
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hal_set_slptr_low();
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// delay_us(TIME_SLEEP_TO_TRX_OFF);
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RF230_sleeping=0;
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} else {
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/* If on, do periodic calibration. See clock.c */
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if (rf230_calibrate) {
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hal_subregister_write(SR_PLL_CF_START,1); //takes 80us max
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hal_subregister_write(SR_PLL_DCU_START,1); //takes 6us, concurrently
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rf230_calibrate=0;
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rf230_calibrated=1;
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delay_us(80); //?
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}
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}
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/* Wait for any previous operation or state transition to finish */
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@ -649,12 +792,19 @@ rf230_transmit(unsigned short payload_len)
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#if RF230_CONF_TIMESTAMPS
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rtimer_clock_t txtime = timesynch_time();
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#endif /* RF230_CONF_TIMESTAMPS */
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#if defined(__AVR_ATmega128RFA1__)
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/* No interrupts across frame download! */
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cli();
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/* slow down the transmit? */
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// delay_us(500);
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#endif
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/* Toggle the SLP_TR pin to initiate the frame transmission */
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hal_set_slptr_high();
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hal_set_slptr_low();
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hal_frame_write(buffer, total_len);
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#if defined(__AVR_ATmega128RFA1__)
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sei();
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#endif
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PRINTF("rf230_transmit:\n");
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#if DEBUG>1
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/* Note the dumped packet will have a zero checksum unless compiled with RF230_CONF_CHECKSUM
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@ -984,14 +1134,14 @@ if (RF230_receive_on) {
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pending = 1;
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#if RADIOSTATS
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#if RADIOSTATS //TODO:This will double count buffered packets
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RF230_receivepackets++;
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#endif
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#if RADIOALWAYSON
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} else {
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DEBUGFLOW('-');
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rxframe.length=0;
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rxframe[rxframe_head].length=0;
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}
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#endif
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return 1;
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@ -1048,7 +1198,7 @@ PROCESS_THREAD(rf230_process, ev, data)
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}
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/* Get packet from Radio if any, else return zero.
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* The two-byte checksum is appended but the returned length does not include it.
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* At present the last frame is buffered in the interrupt routine so this routine
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* Frames are buffered in the interrupt routine so this routine
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* does not access the hardware or change its status
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*/
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/*---------------------------------------------------------------------------*/
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@ -1066,7 +1216,7 @@ rf230_read(void *buf, unsigned short bufsize)
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struct timestamp t;
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#endif /* RF230_CONF_TIMESTAMPS */
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/* The length includes the twp-byte checksum but not the LQI byte */
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len=rxframe.length;
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len=rxframe[rxframe_head].length;
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if (len==0) {
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#if RADIOALWAYSON && DEBUGFLOWSIZE
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if (RF230_receive_on==0) {if (debugflow[debugflowsize-1]!='z') DEBUGFLOW('z');} //cxmac calls with radio off?
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@ -1088,13 +1238,13 @@ if (RF230_receive_on) {
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rf230_time_of_departure = 0;
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#endif /* RF230_CONF_TIMESTAMPS */
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// PRINTSHORT("r%d",rxframe.length);
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PRINTF("rf230_read: %u bytes lqi %u crc %u\n",rxframe.length,rxframe.lqi,rxframe.crc);
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// PRINTSHORT("r%d",rxframe[rxframe_head].length);
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PRINTF("rf230_read: %u bytes lqi %u crc %u\n",rxframe[rxframe_head].length,rxframe[rxframe_head].lqi,rxframe[rxframe_head].crc);
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#if DEBUG>1
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{
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uint8_t i;
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PRINTF("0000");
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for (i=0;i<rxframe.length;i++) PRINTF(" %02x",rxframe.data[i]);
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for (i=0;i<rxframe[rxframe_head].length;i++) PRINTF(" %02x",rxframe[rxframe_head].data[i]);
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PRINTF("\n");
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}
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#endif
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@ -1129,11 +1279,16 @@ if (RF230_receive_on) {
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return 0;
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}
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/* Transfer the frame, stripping the footer, but copying the checksum */
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framep=&(rxframe.data[0]);
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framep=&(rxframe[rxframe_head].data[0]);
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memcpy(buf,framep,len-AUX_LEN+CHECKSUM_LEN);
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rf230_last_correlation = rxframe[rxframe_head].lqi;
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/* Clear the length field to allow buffering of the next packet */
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rxframe.length=0;
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rxframe[rxframe_head].length=0;
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rxframe_head++;if (rxframe_head >= RF230_CONF_RX_BUFFERS) rxframe_head=0;
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/* If another packet has been buffered, schedule another receive poll */
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if (rxframe[rxframe_head].length) rf230_interrupt();
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/* Point to the checksum */
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framep+=len-AUX_LEN;
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#if RF230_CONF_CHECKSUM
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@ -1164,14 +1319,15 @@ if (RF230_receive_on) {
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rf230_last_rssi = rf230_get_raw_rssi();
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#else //faster
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#if RF230_CONF_AUTOACK
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rf230_last_rssi = hal_subregister_read(SR_ED_LEVEL); //0-84 resolution 1 dB
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// rf230_last_rssi = hal_subregister_read(SR_ED_LEVEL); //0-84 resolution 1 dB
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rf230_last_rssi = hal_register_read(RG_PHY_ED_LEVEL); //0-84, resolution 1 dB
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#else
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/* last_rssi will have been set at RX_START interrupt */
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// rf230_last_rssi = 3*hal_subregister_read(SR_RSSI); //0-28 resolution 3 dB
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#endif
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#endif /* speed vs. generality */
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rf230_last_correlation = rxframe.lqi;
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// rf230_last_correlation = rxframe[rxframe_head].lqi;
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packetbuf_set_attr(PACKETBUF_ATTR_RSSI, rf230_last_rssi);
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packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, rf230_last_correlation);
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@ -1251,7 +1407,8 @@ rf230_get_raw_rssi(void)
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/* The rssi register is multiplied by 3 to a consistent value from either register */
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state=radio_get_trx_state();
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if ((state==RX_AACK_ON) || (state==BUSY_RX_AACK)) {
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rssi = hal_subregister_read(SR_ED_LEVEL); //0-84, resolution 1 dB
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// rssi = hal_subregister_read(SR_ED_LEVEL); //0-84, resolution 1 dB
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rssi = hal_register_read(RG_PHY_ED_LEVEL); //0-84, resolution 1 dB
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} else {
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#if 0 // 3-clock shift and add is faster on machines with no hardware multiply
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/* avr-gcc may have an -Os bug that uses the general subroutine for multiplying by 3 */
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