removed old include directory.
This commit is contained in:
Mariano Alvira
parent
1b4dd3b4dc
commit
e9d8dbe5c5
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#ifndef CRM_H
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#define CRM_H
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#define CRM_BASE (0x80003000)
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#define CRM_SYS_CNTL (CRM_BASE+0x00)
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#define CRM_WU_CNTL (CRM_BASE+0x04)
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#define CRM_SLEEP_CNTL (CRM_BASE+0x08)
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#define CRM_BS_CNTL (CRM_BASE+0x0c)
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#define CRM_COP_CNTL (CRM_BASE+0x10)
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#define CRM_COP_SERVICE (CRM_BASE+0x14)
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#define CRM_STATUS (CRM_BASE+0x18)
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#define CRM_MOD_STATUS (CRM_BASE+0x1c)
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#define CRM_WU_COUNT (CRM_BASE+0x20)
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#define CRM_WU_TIMEOUT (CRM_BASE+0x24)
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#define CRM_RTC_COUNT (CRM_BASE+0x28)
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#define CRM_RTC_TIMEOUT (CRM_BASE+0x2c)
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#define CRM_CAL_CNTL (CRM_BASE+0x34)
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#define CRM_CAL_COUNT (CRM_BASE+0x38)
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#define CRM_RINGOSC_CNTL (CRM_BASE+0x3c)
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#define CRM_XTAL_CNTL (CRM_BASE+0x40)
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#define CRM_XTAL32_CNTL (CRM_BASE+0x44)
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#define CRM_VREG_CNTL (CRM_BASE+0x48)
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#define CRM_SW_RST (CRM_BASE+0x50)
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/* wu_cntl bit locations */
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#define EXT_WU_IEN 20 /* 4 bits */
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#define EXT_WU_EN 4 /* 4 bits */
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#define EXT_WU_EDGE 8 /* 4 bits */
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#define EXT_WU_POL 12 /* 4 bits */
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/* status bit locations */
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#define EXT_WU_EVT 4 /* 4 bits */
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#define enable_wu_en(k) (set_bit(reg32(CRM_WU_CNTL),(EXT_WU_EN+k-4)))
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#endif
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@ -1,143 +0,0 @@
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/************************************************************************************
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* This file holds type definitions that maps the standard c-types into types
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* with guaranteed sizes. The types are target/platform specific and must be edited
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* for each new target/platform.
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*
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* The header file also provides definitions for TRUE, FALSE and NULL.
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*
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* (c) Copyright 2006, Freescale Semiconductor, Inc. All rights reserved.
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*
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*
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* No part of this document must be reproduced in any form - including copied,
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* transcribed, printed or by any electronic means - without specific written
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* permission from Freescale Semiconductor.
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*************************************************************************************/
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#ifndef _EMBEDDEDTYPES_H_
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#define _EMBEDDEDTYPES_H_
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/************************************************************************************
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*
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* TYPE DEFINITIONS
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*
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************************************************************************************/
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typedef signed char int8_t;
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typedef unsigned char uint8_t;
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typedef signed short int16_t;
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typedef unsigned short uint16_t;
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typedef signed long int32_t;
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typedef unsigned long uint32_t;
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typedef signed long long int64_t;
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typedef unsigned long long uint64_t;
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typedef signed char intn8_t;
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typedef unsigned char uintn8_t;
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typedef signed short intn16_t;
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typedef unsigned short uintn16_t;
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typedef signed long intn32_t;
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typedef unsigned long uintn32_t;
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typedef signed long long intn64_t;
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typedef unsigned long long uintn64_t;
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/* boolean types */
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typedef uint8_t bool_t;
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typedef uintn8_t booln_t;
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/* used for indexing into an array in the most efficient manner for the platform */
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typedef uint8_t index_t;
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#define BIT0 0x00000001UL
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#define BIT1 0x00000002UL
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#define BIT2 0x00000004UL
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#define BIT3 0x00000008UL
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#define BIT4 0x00000010UL
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#define BIT5 0x00000020UL
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#define BIT6 0x00000040UL
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#define BIT7 0x00000080UL
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#define BIT8 0x00000100UL
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#define BIT9 0x00000200UL
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#define BIT10 0x00000400UL
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#define BIT11 0x00000800UL
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#define BIT12 0x00001000UL
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#define BIT13 0x00002000UL
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#define BIT14 0x00004000UL
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#define BIT15 0x00008000UL
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#define BIT16 0x00010000UL
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#define BIT17 0x00020000UL
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#define BIT18 0x00040000UL
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#define BIT19 0x00080000UL
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#define BIT20 0x00100000UL
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#define BIT21 0x00200000UL
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#define BIT22 0x00400000UL
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#define BIT23 0x00800000UL
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#define BIT24 0x01000000UL
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#define BIT25 0x02000000UL
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#define BIT26 0x04000000UL
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#define BIT27 0x08000000UL
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#define BIT28 0x10000000UL
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#define BIT29 0x20000000UL
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#define BIT30 0x40000000UL
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#define BIT31 0x80000000UL
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#define TRUE 1
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#define FALSE 0
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#ifndef NULL
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#define NULL (( void * )( 0 ))
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#endif
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/* indicate endian-ness of this MCU */
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#define gBigEndian_c FALSE
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typedef uint32_t zbClock32_t;
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typedef uint32_t zbClock24_t;
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typedef uint16_t zbClock16_t;
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/* common macros to reduce code size in S08 */
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#if (gBigEndian_c)
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#define IsEqual2Bytes(aVal1, aVal2) (*((uint16_t *)(aVal1)) == *((uint16_t *)(aVal2)))
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#define Copy2Bytes(aVal1, aVal2) (*((uint16_t *)(aVal1)) = *((uint16_t *)(aVal2)))
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#define Set2Bytes(aVal1, iVal2) (*((uint16_t *)(aVal1)) = (iVal2))
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#define IsEqual2BytesInt(aVal1, iVal2) (*((uint16_t *)(aVal1)) == (iVal2))
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#define TwoBytesToUint16(aVal) ( *((uint16_t *)(aVal)) )
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#define FourBytesToUint32(aVal) ( *((uint32_t *)(aVal)) )
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#define TwoBytes2Byte(aVal) ( (uint8_t)( *( ( uint16_t * )(aVal) ) ) )
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#define Cmp2BytesToZero(aVal) (!( TwoBytesToUint16(aVal) ))
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#define Inc4Bytes(aVal1, iVal2) ( *((uint32_t *)(aVal1)) += (iVal2))
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#else
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#define Copy2Bytes(aVal1, aVal2) (FLib_MemCpy((void *)aVal1,(void *) aVal2, 2))
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void Set2Bytes(void *ptr, uint16_t val);
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bool_t IsEqual2BytesInt(void *ptr, uint16_t val);
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//#define Set2Bytes(aVal1, iVal2) (*((uint16_t *)(aVal1)) = (iVal2))
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//#define IsEqual2BytesInt(aVal1, iVal2) (*((uint16_t *)(aVal1)) == (iVal2))
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#define TwoBytesToUint16(aVal) ( ((uint16_t)(*((uint8_t *)(aVal))))|(((uint16_t)(*(((uint8_t *)(aVal))+1)))<<8) )
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#define FourBytesToUint32(aVal) ( ((uint32_t)TwoBytesToUint16(aVal))|(((uint32_t)TwoBytesToUint16(((uint8_t*)aVal)+2))<<16) )
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#define TwoBytes2Byte(aVal) ( (uint8_t)( *( ( uint8_t * )(aVal) ) ) )
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#define Cmp2BytesToZero(aVal) (!( TwoBytesToUint16(aVal) ))
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void Inc4Bytes(uint8_t* aVal1, uint32_t Val2);
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#define IsEqual2Bytes(aVal1, aVal2) (TwoBytesToUint16(aVal1) == TwoBytesToUint16(aVal2))
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#endif /* #if (gBigEndian_c) */
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/* allow for routines/variables to be static or not at compile-time. */
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#define STATIC
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/* add assert codes if needed. Calls assert function. */
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typedef uint8_t assertCode_t;
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void BeeAppAssert(assertCode_t code);
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#define gAssertCode_NoTasks_c 0x01 /* not enough tasks. Increase gTsMaxTasks_c */
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#define gAssertCode_NoTimers_c 0x02 /* not enough timers. Increase gTmrApplicationTimers_c */
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#define gAssertCode_PageTooBig_c 0x04 /* An NVM page is to big to be stored. */
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#define gMaxIndex_c 0xfe
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#endif /* _EMBEDDEDTYPES_H_ */
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@ -1,272 +0,0 @@
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/*
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* Defines and Macros for Interrupt-Service-Routines
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* collected and partly created by
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* Martin Thomas <mthomas@rhrk.uni-kl.de>
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*
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* Copyright 2005 M. Thomas
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* No guarantees, warrantees, or promises, implied or otherwise.
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* May be used for hobby or commercial purposes provided copyright
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* notice remains intact.
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*/
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#ifndef interrupt_utils_
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#define interrupt_utils_
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/*
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The following defines are usefull for
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interrupt service routine declarations.
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*/
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/*
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RAMFUNC
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Attribute which defines a function to be located
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in memory section .fastrun and called via "long calls".
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See linker-skript and startup-code to see how the
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.fastrun-section is handled.
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The definition is not only useful for ISRs but since
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ISRs should be executed fast the macro is defined in
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this header.
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*/
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#define RAMFUNC __attribute__ ((long_call, section (".fastrun")))
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/*
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INTFUNC
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standard attribute for arm-elf-gcc which marks
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a function as ISR (for the VIC). Since gcc seems
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to produce wrong code if this attribute is used in
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thumb/thumb-interwork the attribute should only be
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used for "pure ARM-mode" binaries.
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*/
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#define INTFUNC __attribute__ ((interrupt("IRQ")))
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/*
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NACKEDFUNC
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gcc will not add any code to a function declared
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"nacked". The user has to take care to save registers
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and add the needed code for ISR functions. Some
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macros for this tasks are provided below.
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*/
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#define NACKEDFUNC __attribute__((naked))
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/******************************************************************************
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*
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* MACRO Name: ISR_STORE()
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*
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* Description:
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* This MACRO is used upon entry to an ISR with interrupt nesting.
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* Should be used together with ISR_ENABLE_NEST(). The MACRO
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* performs the following steps:
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*
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* 1 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
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*
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*****************************************************************************/
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#define ISR_STORE() asm volatile( \
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"STMDB SP!,{R0-R12,LR}\n" )
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/******************************************************************************
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*
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* MACRO Name: ISR_RESTORE()
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*
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* Description:
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* This MACRO is used upon exit from an ISR with interrupt nesting.
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* Should be used together with ISR_DISABLE_NEST(). The MACRO
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* performs the following steps:
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*
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* 1 - Load the non-banked registers r0-r12 and lr from the IRQ stack.
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* 2 - Adjusts resume adress
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*
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*****************************************************************************/
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#define ISR_RESTORE() asm volatile( \
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"LDMIA SP!,{R0-R12,LR}\n" \
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"SUBS R15,R14,#0x0004\n" )
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/******************************************************************************
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*
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* MACRO Name: ISR_ENABLE_NEST()
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*
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* Description:
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* This MACRO is used upon entry from an ISR with interrupt nesting.
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* Should be used after ISR_STORE.
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*
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*****************************************************************************/
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#define ISR_ENABLE_NEST() asm volatile( \
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"MRS LR, SPSR \n" \
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"STMFD SP!, {LR} \n" \
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"MSR CPSR_c, #0x1f \n" \
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"STMFD SP!, {LR} " )
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/******************************************************************************
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*
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* MACRO Name: ISR_DISABLE_NEST()
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*
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* Description:
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* This MACRO is used upon entry from an ISR with interrupt nesting.
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* Should be used before ISR_RESTORE.
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*
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*****************************************************************************/
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#define ISR_DISABLE_NEST() asm volatile( \
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"LDMFD SP!, {LR} \n" \
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"MSR CPSR_c, #0x92 \n" \
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"LDMFD SP!, {LR} \n" \
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"MSR SPSR_cxsf, LR \n" )
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/*
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* The following marcos are from the file "armVIC.h" by:
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*
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* Copyright 2004, R O SoftWare
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* No guarantees, warrantees, or promises, implied or otherwise.
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* May be used for hobby or commercial purposes provided copyright
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* notice remains intact.
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*
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*/
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/******************************************************************************
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*
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* MACRO Name: ISR_ENTRY()
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*
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* Description:
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* This MACRO is used upon entry to an ISR. The current version of
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* the gcc compiler for ARM does not produce correct code for
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* interrupt routines to operate properly with THUMB code. The MACRO
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* performs the following steps:
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*
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* 1 - Adjust address at which execution should resume after servicing
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* ISR to compensate for IRQ entry
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* 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
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* 3 - Get the status of the interrupted program is in SPSR.
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* 4 - Push it onto the IRQ stack as well.
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*
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*****************************************************************************/
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#define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \
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" stmfd sp!,{r0-r12,lr}\n" \
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" mrs r1, spsr\n" \
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" stmfd sp!,{r1}")
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/******************************************************************************
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*
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* MACRO Name: ISR_EXIT()
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*
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* Description:
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* This MACRO is used to exit an ISR. The current version of the gcc
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* compiler for ARM does not produce correct code for interrupt
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* routines to operate properly with THUMB code. The MACRO performs
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* the following steps:
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*
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* 1 - Recover SPSR value from stack
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* 2 - and restore its value
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* 3 - Pop the return address & the saved general registers from
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* the IRQ stack & return
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*
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*****************************************************************************/
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#define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \
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" msr spsr_c,r1\n" \
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" ldmfd sp!,{r0-r12,pc}^")
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/******************************************************************************
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*
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* Function Name: disableIRQ()
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*
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* Description:
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* This function sets the IRQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned disableIRQ(void);
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/******************************************************************************
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|
||||||
*
|
|
||||||
* Function Name: enableIRQ()
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* This function clears the IRQ disable bit in the status register
|
|
||||||
*
|
|
||||||
* Calling Sequence:
|
|
||||||
* void
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* previous value of CPSR
|
|
||||||
*
|
|
||||||
*****************************************************************************/
|
|
||||||
unsigned enableIRQ(void);
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Function Name: restoreIRQ()
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* This function restores the IRQ disable bit in the status register
|
|
||||||
* to the value contained within passed oldCPSR
|
|
||||||
*
|
|
||||||
* Calling Sequence:
|
|
||||||
* void
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* previous value of CPSR
|
|
||||||
*
|
|
||||||
*****************************************************************************/
|
|
||||||
unsigned restoreIRQ(unsigned oldCPSR);
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Function Name: disableFIQ()
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* This function sets the FIQ disable bit in the status register
|
|
||||||
*
|
|
||||||
* Calling Sequence:
|
|
||||||
* void
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* previous value of CPSR
|
|
||||||
*
|
|
||||||
*****************************************************************************/
|
|
||||||
unsigned disableFIQ(void);
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Function Name: enableFIQ()
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* This function clears the FIQ disable bit in the status register
|
|
||||||
*
|
|
||||||
* Calling Sequence:
|
|
||||||
* void
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* previous value of CPSR
|
|
||||||
*
|
|
||||||
*****************************************************************************/
|
|
||||||
unsigned enableFIQ(void);
|
|
||||||
|
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Function Name: restoreFIQ()
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* This function restores the FIQ disable bit in the status register
|
|
||||||
* to the value contained within passed oldCPSR
|
|
||||||
*
|
|
||||||
* Calling Sequence:
|
|
||||||
* void
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* previous value of CPSR
|
|
||||||
*
|
|
||||||
*****************************************************************************/
|
|
||||||
unsigned restoreFIQ(unsigned oldCPSR);
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
@ -1,29 +0,0 @@
|
||||||
#ifndef __SYS_INTERRUPT_H
|
|
||||||
#define __SYS_INTERRUPT_H
|
|
||||||
|
|
||||||
/* Returns true if it handled an active interrupt */
|
|
||||||
typedef int (*SystemInterruptFunc)();
|
|
||||||
|
|
||||||
typedef struct _SystemInterruptHandler SystemInterruptHandler;
|
|
||||||
struct _SystemInterruptHandler
|
|
||||||
{
|
|
||||||
SystemInterruptHandler *next;
|
|
||||||
SystemInterruptFunc handler;
|
|
||||||
};
|
|
||||||
|
|
||||||
void
|
|
||||||
sys_interrupt_enable();
|
|
||||||
|
|
||||||
void
|
|
||||||
sys_interrupt_disable();
|
|
||||||
|
|
||||||
void
|
|
||||||
sys_interrupt_append_handler(SystemInterruptHandler *handler);
|
|
||||||
|
|
||||||
void
|
|
||||||
sys_interrupt_prepend_handler(SystemInterruptHandler *handler);
|
|
||||||
|
|
||||||
void
|
|
||||||
sys_interrupt_remove_handler(SystemInterruptHandler *handler);
|
|
||||||
|
|
||||||
#endif /* __SYS_INTERRUPT_H */
|
|
||||||
|
|
@ -1,84 +0,0 @@
|
||||||
/* Timer registers are all 16-bit wide with 16-bit access only */
|
|
||||||
#define TMR_OFFSET (0x20)
|
|
||||||
#define TMR_BASE (0x80007000)
|
|
||||||
#define TMR0_BASE (TMR_BASE)
|
|
||||||
#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
|
|
||||||
#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
|
|
||||||
#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
|
|
||||||
|
|
||||||
#define TMR_REGOFF_COMP1 (0x0)
|
|
||||||
#define TMR_REGOFF_COMP2 (0x2)
|
|
||||||
#define TMR_REGOFF_CAPT (0x4)
|
|
||||||
#define TMR_REGOFF_LOAD (0x6)
|
|
||||||
#define TMR_REGOFF_HOLD (0x8)
|
|
||||||
#define TMR_REGOFF_CNTR (0xa)
|
|
||||||
#define TMR_REGOFF_CTRL (0xc)
|
|
||||||
#define TMR_REGOFF_SCTRL (0xe)
|
|
||||||
#define TMR_REGOFF_CMPLD1 (0x10)
|
|
||||||
#define TMR_REGOFF_CMPLD2 (0x12)
|
|
||||||
#define TMR_REGOFF_CSCTRL (0x14)
|
|
||||||
#define TMR_REGOFF_ENBL (0x1e)
|
|
||||||
|
|
||||||
/* one enable register to rule them all */
|
|
||||||
#define TMR_ENBL TMR0_BASE + TMR_REGOFF_ENBL
|
|
||||||
|
|
||||||
/* Timer 0 registers */
|
|
||||||
#define TMR0_COMP1 (TMR0_BASE + TMR_REGOFF_COMP1)
|
|
||||||
#define TMR0_COMP_UP TMR0_COMP1
|
|
||||||
#define TMR0_COMP2 (TMR0_BASE + TMR_REGOFF_COMP2)
|
|
||||||
#define TMR0_COMP_DOWN TMR0_COMP2
|
|
||||||
#define TMR0_CAPT (TMR0_BASE + TMR_REGOFF_CAPT)
|
|
||||||
#define TMR0_LOAD (TMR0_BASE + TMR_REGOFF_LOAD)
|
|
||||||
#define TMR0_HOLD (TMR0_BASE + TMR_REGOFF_HOLD)
|
|
||||||
#define TMR0_CNTR (TMR0_BASE + TMR_REGOFF_CTRL)
|
|
||||||
#define TMR0_CTRL (TMR0_BASE + TMR_REGOFF_CTRL)
|
|
||||||
#define TMR0_SCTRL (TMR0_BASE + TMR_REGOFF_SCTRL)
|
|
||||||
#define TMR0_CMPLD1 (TMR0_BASE + TMR_REGOFF_CMPLD1)
|
|
||||||
#define TMR0_CMPLD2 (TMR0_BASE + TMR_REGOFF_CMPLD2)
|
|
||||||
#define TMR0_CSCTRL (TMR0_BASE + TMR_REGOFF_CSCTRL)
|
|
||||||
|
|
||||||
/* Timer 1 registers */
|
|
||||||
#define TMR1_COMP1 (TMR1_BASE + TMR_REGOFF_COMP1)
|
|
||||||
#define TMR1_COMP_UP TMR1_COMP1
|
|
||||||
#define TMR1_COMP2 (TMR1_BASE + TMR_REGOFF_COMP2)
|
|
||||||
#define TMR1_COMP_DOWN TMR1_COMP2
|
|
||||||
#define TMR1_CAPT (TMR1_BASE + TMR_REGOFF_CAPT)
|
|
||||||
#define TMR1_LOAD (TMR1_BASE + TMR_REGOFF_LOAD)
|
|
||||||
#define TMR1_HOLD (TMR1_BASE + TMR_REGOFF_HOLD)
|
|
||||||
#define TMR1_CNTR (TMR1_BASE + TMR_REGOFF_CTRL)
|
|
||||||
#define TMR1_CTRL (TMR1_BASE + TMR_REGOFF_CTRL)
|
|
||||||
#define TMR1_SCTRL (TMR1_BASE + TMR_REGOFF_SCTRL)
|
|
||||||
#define TMR1_CMPLD1 (TMR1_BASE + TMR_REGOFF_CMPLD1)
|
|
||||||
#define TMR1_CMPLD2 (TMR1_BASE + TMR_REGOFF_CMPLD2)
|
|
||||||
#define TMR1_CSCTRL (TMR1_BASE + TMR_REGOFF_CSCTRL)
|
|
||||||
|
|
||||||
/* Timer 2 registers */
|
|
||||||
#define TMR2_COMP1 (TMR2_BASE + TMR_REGOFF_COMP1)
|
|
||||||
#define TMR2_COMP_UP TMR2_COMP1
|
|
||||||
#define TMR2_COMP2 (TMR2_BASE + TMR_REGOFF_COMP2)
|
|
||||||
#define TMR2_COMP_DOWN TMR2_COMP2
|
|
||||||
#define TMR2_CAPT (TMR2_BASE + TMR_REGOFF_CAPT)
|
|
||||||
#define TMR2_LOAD (TMR2_BASE + TMR_REGOFF_LOAD)
|
|
||||||
#define TMR2_HOLD (TMR2_BASE + TMR_REGOFF_HOLD)
|
|
||||||
#define TMR2_CNTR (TMR2_BASE + TMR_REGOFF_CTRL)
|
|
||||||
#define TMR2_CTRL (TMR2_BASE + TMR_REGOFF_CTRL)
|
|
||||||
#define TMR2_SCTRL (TMR2_BASE + TMR_REGOFF_SCTRL)
|
|
||||||
#define TMR2_CMPLD1 (TMR2_BASE + TMR_REGOFF_CMPLD1)
|
|
||||||
#define TMR2_CMPLD2 (TMR2_BASE + TMR_REGOFF_CMPLD2)
|
|
||||||
#define TMR2_CSCTRL (TMR2_BASE + TMR_REGOFF_CSCTRL)
|
|
||||||
|
|
||||||
/* Timer 3 registers */
|
|
||||||
#define TMR3_COMP1 (TMR3_BASE + TMR_REGOFF_COMP1)
|
|
||||||
#define TMR3_COMP_UP TMR3_COMP1
|
|
||||||
#define TMR3_COMP2 (TMR3_BASE + TMR_REGOFF_COMP2)
|
|
||||||
#define TMR3_COMP_DOWN TMR3_COMP2
|
|
||||||
#define TMR3_CAPT (TMR3_BASE + TMR_REGOFF_CAPT)
|
|
||||||
#define TMR3_LOAD (TMR3_BASE + TMR_REGOFF_LOAD)
|
|
||||||
#define TMR3_HOLD (TMR3_BASE + TMR_REGOFF_HOLD)
|
|
||||||
#define TMR3_CNTR (TMR3_BASE + TMR_REGOFF_CTRL)
|
|
||||||
#define TMR3_CTRL (TMR3_BASE + TMR_REGOFF_CTRL)
|
|
||||||
#define TMR3_SCTRL (TMR3_BASE + TMR_REGOFF_SCTRL)
|
|
||||||
#define TMR3_CMPLD1 (TMR3_BASE + TMR_REGOFF_CMPLD1)
|
|
||||||
#define TMR3_CMPLD2 (TMR3_BASE + TMR_REGOFF_CMPLD2)
|
|
||||||
#define TMR3_CSCTRL (TMR3_BASE + TMR_REGOFF_CSCTRL)
|
|
||||||
|
|
||||||
|
|
@ -1,12 +0,0 @@
|
||||||
#ifndef UTILS_H
|
|
||||||
#define UTILS_H
|
|
||||||
|
|
||||||
#define reg32(x) (*(volatile uint32_t *)(x))
|
|
||||||
#define reg16(x) (*(volatile uint16_t *)(x))
|
|
||||||
|
|
||||||
#define bit(bit) (1<<bit)
|
|
||||||
#define bit_is_set(val,bit) (((val & (1<<bit)) >> bit) == 1)
|
|
||||||
#define clear_bit(val,bit) (val=(val & ~(1<<bit)))
|
|
||||||
#define set_bit(val,bit) (val=(val | (1<<bit)))
|
|
||||||
|
|
||||||
#endif
|
|
||||||
Loading…
Reference in a new issue