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Update to latest overrides and patches

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This commit is contained in:
George Oikonomou 2016-11-06 21:14:09 +00:00
parent db54175d8d
commit e73ac7d26f
2 changed files with 64 additions and 15 deletions
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2
cpu/cc26xx-cc13xx/rf-core/prop-mode.c
View file

@ -72,6 +72,7 @@
/*---------------------------------------------------------------------------*/
/* CC13xxware patches */
#include "rf_patches/rf_patch_cpe_genfsk.h"
#include "rf_patches/rf_patch_rfe_genfsk.h"
/*---------------------------------------------------------------------------*/
#include "rf-core/smartrf-settings.h"
/*---------------------------------------------------------------------------*/
@ -895,6 +896,7 @@ on(void)
}
rf_patch_cpe_genfsk();
rf_patch_rfe_genfsk();
if(rf_core_start_rat() != RF_CORE_CMD_OK) {
PRINTF("on: rf_core_start_rat() failed\n");

77
cpu/cc26xx-cc13xx/rf-core/smartrf-settings.c
View file

@ -33,28 +33,75 @@
#include "driverlib/rf_prop_cmd.h"
/*---------------------------------------------------------------------------*/
/* Overrides for CMD_PROP_RADIO_DIV_SETUP */
uint32_t overrides[] =
static uint32_t overrides[] =
{
/* override_synth.xml */
HW32_ARRAY_OVERRIDE(0x6088, 1),
(uint32_t)0x0000001A,
ADI_HALFREG_OVERRIDE(0, 61, 0xF, 0xD),
HW32_ARRAY_OVERRIDE(0x4038, 1),
(uint32_t)0x0000003A,
/*
* override_use_patch_prop_genfsk.xml
* PHY: Use MCE ROM bank 4, RFE RAM patch
*/
MCE_RFE_OVERRIDE(0, 4, 0, 1, 0, 0),
/*
* override_synth_prop_863_930_div5.xml
* Synth: Set recommended RTRIM to 7
*/
HW_REG_OVERRIDE(0x4038, 0x0037),
/* Synth: Set Fref to 4 MHz */
(uint32_t)0x000684A3,
/* Synth: Configure fine calibration setting */
HW_REG_OVERRIDE(0x4020, 0x7F00),
/* Synth: Configure fine calibration setting */
HW_REG_OVERRIDE(0x4064, 0x0040),
(uint32_t)0x684A3,
(uint32_t)0xC0040141,
(uint32_t)0x0533B107,
(uint32_t)0xA480583,
/* Synth: Configure fine calibration setting */
(uint32_t)0xB1070503,
/* Synth: Configure fine calibration setting */
(uint32_t)0x05330523,
/* Synth: Set loop bandwidth after lock to 20 kHz */
(uint32_t)0x0A480583,
/* Synth: Set loop bandwidth after lock to 20 kHz */
(uint32_t)0x7AB80603,
ADI_REG_OVERRIDE(1, 4, 0x1F),
/*
* Synth: Configure VCO LDO
* (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
*/
ADI_REG_OVERRIDE(1, 4, 0x9F),
/* Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1) */
ADI_HALFREG_OVERRIDE(1, 7, 0x4, 0x4),
HW_REG_OVERRIDE(0x6084, 0x35F1),
/* Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering */
(uint32_t)0x02010403,
/* Synth: Configure extra PLL filtering */
(uint32_t)0x00108463,
/* Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us) */
(uint32_t)0x04B00243,
/*
* override_phy_rx_aaf_bw_0xd.xml
* Rx: Set anti-aliasing filter bandwidth to 0xD
* (in ADI0, set IFAMPCTL3[7:4]=0xD)
*/
ADI_HALFREG_OVERRIDE(0, 61, 0xF, 0xD),
/*
* override_phy_gfsk_rx.xml
* Rx: Set LNA bias current trim offset to 3
*/
(uint32_t)0x00038883,
/* Rx: Freeze RSSI on sync found event */
HW_REG_OVERRIDE(0x6084, 0x35F1),
/*
* override_phy_gfsk_pa_ramp_agc_reflevel_0x1a.xml
* Tx: Enable PA ramping (0x41). Rx: Set AGC reference level to 0x1A.
*/
HW_REG_OVERRIDE(0x6088, 0x411A),
/* Tx: Configure PA ramping setting */
HW_REG_OVERRIDE(0x608C, 0x8213),
/*
* override_phy_rx_rssi_offset_5db.xml
* Rx: Set RSSI offset to adjust reported RSSI by +5 dB
*/
(uint32_t)0x00FB88A3,
/* TX power override */
ADI_REG_OVERRIDE(0, 12, 0xF9),
/*
* TX power override
* Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8)
*/
ADI_REG_OVERRIDE(0, 12, 0xF8),
/* Overrides for CRC16 functionality */
(uint32_t)0x943,