cc2538: uart: Make it possible to use several UARTs simultaneously
This avoids the limitation of having a single UART available at runtime, without duplicating code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau
parent
db754a57d7
commit
d93d129da6
12 changed files with 353 additions and 146 deletions
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@ -48,88 +48,220 @@
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#include <stdint.h>
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#include <string.h>
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static int (* input_handler)(unsigned char c);
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/*---------------------------------------------------------------------------*/
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#define UART_RX_PORT_BASE GPIO_PORT_TO_BASE(UART_RX_PORT)
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#define UART_RX_PIN_MASK GPIO_PIN_MASK(UART_RX_PIN)
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#ifndef UART0_RX_PORT
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#define UART0_RX_PORT (-1)
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#endif
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#ifndef UART0_RX_PIN
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#define UART0_RX_PIN (-1)
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#endif
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#if UART0_RX_PORT >= 0 && UART0_RX_PIN < 0 || \
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UART0_RX_PORT < 0 && UART0_RX_PIN >= 0
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#error Both UART0_RX_PORT and UART0_RX_PIN must be valid or invalid
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#endif
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#define UART_TX_PORT_BASE GPIO_PORT_TO_BASE(UART_TX_PORT)
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#define UART_TX_PIN_MASK GPIO_PIN_MASK(UART_TX_PIN)
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#ifndef UART0_TX_PORT
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#define UART0_TX_PORT (-1)
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#endif
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#ifndef UART0_TX_PIN
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#define UART0_TX_PIN (-1)
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#endif
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#if UART0_TX_PORT >= 0 && UART0_TX_PIN < 0 || \
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UART0_TX_PORT < 0 && UART0_TX_PIN >= 0
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#error Both UART0_TX_PORT and UART0_TX_PIN must be valid or invalid
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#endif
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#define UART_CTS_PORT_BASE GPIO_PORT_TO_BASE(UART_CTS_PORT)
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#define UART_CTS_PIN_MASK GPIO_PIN_MASK(UART_CTS_PIN)
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#if UART0_RX_PORT >= 0 && UART0_TX_PORT < 0 || \
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UART0_RX_PORT < 0 && UART0_TX_PORT >= 0
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#error Both UART0_RX and UART0_TX pads must be valid or invalid
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#endif
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#define UART_RTS_PORT_BASE GPIO_PORT_TO_BASE(UART_RTS_PORT)
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#define UART_RTS_PIN_MASK GPIO_PIN_MASK(UART_RTS_PIN)
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/*---------------------------------------------------------------------------*/
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/*
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* Once we know what UART we're on, configure correct values to be written to
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* the correct registers
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*/
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#if UART_BASE==UART_1_BASE
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/* Running, in sleep, in deep sleep, enable the clock for the correct UART */
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#define SYS_CTRL_RCGCUART_UART SYS_CTRL_RCGCUART_UART1
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#define SYS_CTRL_SCGCUART_UART SYS_CTRL_SCGCUART_UART1
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#define SYS_CTRL_DCGCUART_UART SYS_CTRL_DCGCUART_UART1
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#if UART_IN_USE(0) && UART0_RX_PORT < 0
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#error Contiki is configured to use UART0, but its pads are not valid
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#endif
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#define NVIC_INT_UART NVIC_INT_UART1
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#define IOC_PXX_SEL_UART_TXD IOC_PXX_SEL_UART1_TXD
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#define IOC_UARTRXD_UART IOC_UARTRXD_UART1
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#else /* Defaults for UART0 */
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#define SYS_CTRL_RCGCUART_UART SYS_CTRL_RCGCUART_UART0
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#define SYS_CTRL_SCGCUART_UART SYS_CTRL_SCGCUART_UART0
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#define SYS_CTRL_DCGCUART_UART SYS_CTRL_DCGCUART_UART0
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#ifndef UART1_RX_PORT
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#define UART1_RX_PORT (-1)
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#endif
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#ifndef UART1_RX_PIN
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#define UART1_RX_PIN (-1)
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#endif
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#if UART1_RX_PORT >= 0 && UART1_RX_PIN < 0 || \
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UART1_RX_PORT < 0 && UART1_RX_PIN >= 0
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#error Both UART1_RX_PORT and UART1_RX_PIN must be valid or invalid
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#endif
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#define NVIC_INT_UART NVIC_INT_UART0
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#ifndef UART1_TX_PORT
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#define UART1_TX_PORT (-1)
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#endif
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#ifndef UART1_TX_PIN
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#define UART1_TX_PIN (-1)
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#endif
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#if UART1_TX_PORT >= 0 && UART1_TX_PIN < 0 || \
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UART1_TX_PORT < 0 && UART1_TX_PIN >= 0
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#error Both UART1_TX_PORT and UART1_TX_PIN must be valid or invalid
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#endif
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#define IOC_PXX_SEL_UART_TXD IOC_PXX_SEL_UART0_TXD
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#define IOC_UARTRXD_UART IOC_UARTRXD_UART0
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#if UART1_RX_PORT >= 0 && UART1_TX_PORT < 0 || \
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UART1_RX_PORT < 0 && UART1_TX_PORT >= 0
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#error Both UART1_RX and UART1_TX pads must be valid or invalid
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#endif
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#if UART_IN_USE(1) && UART1_RX_PORT < 0
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#error Contiki is configured to use UART1, but its pads are not valid
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#endif
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#ifndef UART1_CTS_PORT
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#define UART1_CTS_PORT (-1)
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#endif
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#ifndef UART1_CTS_PIN
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#define UART1_CTS_PIN (-1)
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#endif
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#if UART1_CTS_PORT >= 0 && UART1_CTS_PIN < 0 || \
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UART1_CTS_PORT < 0 && UART1_CTS_PIN >= 0
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#error Both UART1_CTS_PORT and UART1_CTS_PIN must be valid or invalid
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#endif
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#ifndef UART1_RTS_PORT
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#define UART1_RTS_PORT (-1)
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#endif
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#ifndef UART1_RTS_PIN
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#define UART1_RTS_PIN (-1)
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#endif
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#if UART1_RTS_PORT >= 0 && UART1_RTS_PIN < 0 || \
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UART1_RTS_PORT < 0 && UART1_RTS_PIN >= 0
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#error Both UART1_RTS_PORT and UART1_RTS_PIN must be valid or invalid
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#endif
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/*---------------------------------------------------------------------------*/
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/*
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* Baud rate defines used in uart_init() to set the values of UART_IBRD and
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* UART_FBRD in order to achieve the configured baud rates.
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*/
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#define UART_CLOCK_RATE 16000000 /* 16 MHz */
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#define UART_CTL_HSE_VALUE 0
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#define UART_CTL_VALUE (UART_CTL_RXE | UART_CTL_TXE | (UART_CTL_HSE_VALUE << 5))
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/* DIV_ROUND() divides integers while avoiding a rounding error: */
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#define DIV_ROUND(num, denom) (((num) + (denom) / 2) / (denom))
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#define BAUD2BRD(baud) DIV_ROUND(UART_CLOCK_RATE << (UART_CTL_HSE_VALUE + 2), (baud))
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#define BAUD2IBRD(baud) (BAUD2BRD(baud) >> 6)
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#define BAUD2FBRD(baud) (BAUD2BRD(baud) & 0x3f)
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/*---------------------------------------------------------------------------*/
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typedef struct {
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int8_t port;
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int8_t pin;
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} uart_pad_t;
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typedef struct {
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uint32_t sys_ctrl_rcgcuart_uart;
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uint32_t sys_ctrl_scgcuart_uart;
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uint32_t sys_ctrl_dcgcuart_uart;
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uint32_t base;
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uint32_t ioc_uartrxd_uart;
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uint32_t ioc_pxx_sel_uart_txd;
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uint32_t ibrd;
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uint32_t fbrd;
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uart_pad_t rx;
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uart_pad_t tx;
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uart_pad_t cts;
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uart_pad_t rts;
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uint8_t nvic_int;
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} uart_regs_t;
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/*---------------------------------------------------------------------------*/
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static const uart_regs_t uart_regs[UART_INSTANCE_COUNT] = {
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{
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.sys_ctrl_rcgcuart_uart = SYS_CTRL_RCGCUART_UART0,
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.sys_ctrl_scgcuart_uart = SYS_CTRL_SCGCUART_UART0,
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.sys_ctrl_dcgcuart_uart = SYS_CTRL_DCGCUART_UART0,
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.base = UART_0_BASE,
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.ioc_uartrxd_uart = IOC_UARTRXD_UART0,
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.ioc_pxx_sel_uart_txd = IOC_PXX_SEL_UART0_TXD,
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.ibrd = BAUD2IBRD(UART0_CONF_BAUD_RATE),
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.fbrd = BAUD2FBRD(UART0_CONF_BAUD_RATE),
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.rx = {UART0_RX_PORT, UART0_RX_PIN},
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.tx = {UART0_TX_PORT, UART0_TX_PIN},
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.cts = {-1, -1},
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.rts = {-1, -1},
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.nvic_int = NVIC_INT_UART0
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}, {
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.sys_ctrl_rcgcuart_uart = SYS_CTRL_RCGCUART_UART1,
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.sys_ctrl_scgcuart_uart = SYS_CTRL_SCGCUART_UART1,
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.sys_ctrl_dcgcuart_uart = SYS_CTRL_DCGCUART_UART1,
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.base = UART_1_BASE,
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.ioc_uartrxd_uart = IOC_UARTRXD_UART1,
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.ioc_pxx_sel_uart_txd = IOC_PXX_SEL_UART1_TXD,
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.ibrd = BAUD2IBRD(UART1_CONF_BAUD_RATE),
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.fbrd = BAUD2FBRD(UART1_CONF_BAUD_RATE),
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.rx = {UART1_RX_PORT, UART1_RX_PIN},
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.tx = {UART1_TX_PORT, UART1_TX_PIN},
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.cts = {UART1_CTS_PORT, UART1_CTS_PIN},
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.rts = {UART1_RTS_PORT, UART1_RTS_PIN},
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.nvic_int = NVIC_INT_UART1
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}
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};
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static int (* input_handler[UART_INSTANCE_COUNT])(unsigned char c);
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/*---------------------------------------------------------------------------*/
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static void
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reset(void)
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reset(uint32_t uart_base)
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{
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uint32_t lchr;
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/* Make sure the UART is disabled before trying to configure it */
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REG(UART_BASE | UART_CTL) = UART_CTL_VALUE;
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REG(uart_base | UART_CTL) = UART_CTL_VALUE;
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/* Clear error status */
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REG(UART_BASE | UART_ECR) = 0xFF;
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REG(uart_base | UART_ECR) = 0xFF;
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/* Store LCHR configuration */
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lchr = REG(UART_BASE | UART_LCRH);
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lchr = REG(uart_base | UART_LCRH);
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/* Flush FIFOs by clearing LCHR.FEN */
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REG(UART_BASE | UART_LCRH) = 0;
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REG(uart_base | UART_LCRH) = 0;
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/* Restore LCHR configuration */
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REG(UART_BASE | UART_LCRH) = lchr;
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REG(uart_base | UART_LCRH) = lchr;
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/* UART Enable */
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REG(UART_BASE | UART_CTL) |= UART_CTL_UARTEN;
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REG(uart_base | UART_CTL) |= UART_CTL_UARTEN;
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}
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/*---------------------------------------------------------------------------*/
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static bool
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permit_pm1(void)
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{
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/* Note: UART_FR.TXFE reads 0 if the UART clock is gated. */
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return (REG(SYS_CTRL_RCGCUART) & SYS_CTRL_RCGCUART_UART) == 0 ||
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(REG(UART_BASE | UART_FR) & UART_FR_TXFE) != 0;
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const uart_regs_t *regs;
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for(regs = &uart_regs[0]; regs < &uart_regs[UART_INSTANCE_COUNT]; regs++) {
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/* Note: UART_FR.TXFE reads 0 if the UART clock is gated. */
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if((REG(SYS_CTRL_RCGCUART) & regs->sys_ctrl_rcgcuart_uart) != 0 &&
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(REG(regs->base | UART_FR) & UART_FR_TXFE) == 0) {
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return false;
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}
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}
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return true;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_init(void)
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uart_init(uint8_t uart)
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{
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const uart_regs_t *regs;
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if(uart >= UART_INSTANCE_COUNT) {
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return;
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}
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regs = &uart_regs[uart];
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if(regs->rx.port < 0 || regs->tx.port < 0) {
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return;
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}
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lpm_register_peripheral(permit_pm1);
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/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
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REG(SYS_CTRL_RCGCUART) |= SYS_CTRL_RCGCUART_UART;
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REG(SYS_CTRL_SCGCUART) |= SYS_CTRL_SCGCUART_UART;
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REG(SYS_CTRL_DCGCUART) |= SYS_CTRL_DCGCUART_UART;
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REG(SYS_CTRL_RCGCUART) |= regs->sys_ctrl_rcgcuart_uart;
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REG(SYS_CTRL_SCGCUART) |= regs->sys_ctrl_scgcuart_uart;
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REG(SYS_CTRL_DCGCUART) |= regs->sys_ctrl_dcgcuart_uart;
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/* Run on SYS_DIV */
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REG(UART_BASE | UART_CC) = 0;
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REG(regs->base | UART_CC) = 0;
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/*
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* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
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@ -139,91 +271,116 @@ uart_init(void)
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*
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* (port << 3) + pin
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*/
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REG(IOC_UARTRXD_UART) = (UART_RX_PORT << 3) + UART_RX_PIN;
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REG(regs->ioc_uartrxd_uart) = (regs->rx.port << 3) + regs->rx.pin;
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/*
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* Pad Control for the TX pin:
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* - Set function to UART0 TX
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* - Set function to UARTn TX
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* - Output Enable
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*/
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ioc_set_sel(UART_TX_PORT, UART_TX_PIN, IOC_PXX_SEL_UART_TXD);
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ioc_set_over(UART_TX_PORT, UART_TX_PIN, IOC_OVERRIDE_OE);
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ioc_set_sel(regs->tx.port, regs->tx.pin, regs->ioc_pxx_sel_uart_txd);
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ioc_set_over(regs->tx.port, regs->tx.pin, IOC_OVERRIDE_OE);
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/* Set RX and TX pins to peripheral mode */
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GPIO_PERIPHERAL_CONTROL(UART_TX_PORT_BASE, UART_TX_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(UART_RX_PORT_BASE, UART_RX_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->tx.port),
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GPIO_PIN_MASK(regs->tx.pin));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
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GPIO_PIN_MASK(regs->rx.pin));
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if(regs->cts.port >= 0 || regs->rts.port >= 0) {
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/* TODO Hardware flow control */
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}
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/*
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* UART Interrupt Masks:
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* Acknowledge RX and RX Timeout
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* Acknowledge Framing, Overrun and Break Errors
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*/
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REG(UART_BASE | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
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REG(UART_BASE | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
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REG(regs->base | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
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REG(regs->base | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
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REG(UART_BASE | UART_IFLS) =
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REG(regs->base | UART_IFLS) =
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UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
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/* Make sure the UART is disabled before trying to configure it */
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REG(UART_BASE | UART_CTL) = UART_CTL_VALUE;
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REG(regs->base | UART_CTL) = UART_CTL_VALUE;
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/* Baud Rate Generation */
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uart_set_baudrate(UART_CONF_BAUD_RATE);
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REG(regs->base | UART_IBRD) = regs->ibrd;
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REG(regs->base | UART_FBRD) = regs->fbrd;
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/* UART Control: 8N1 with FIFOs */
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REG(UART_BASE | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
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REG(regs->base | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
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/* UART Enable */
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REG(UART_BASE | UART_CTL) |= UART_CTL_UARTEN;
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REG(regs->base | UART_CTL) |= UART_CTL_UARTEN;
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/* Enable UART0 Interrupts */
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nvic_interrupt_enable(NVIC_INT_UART);
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nvic_interrupt_enable(regs->nvic_int);
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_set_input(int (* input)(unsigned char c))
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uart_set_input(uint8_t uart, int (* input)(unsigned char c))
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{
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input_handler = input;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_write_byte(uint8_t b)
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{
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/* Block if the TX FIFO is full */
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while(REG(UART_BASE | UART_FR) & UART_FR_TXFF);
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if(uart >= UART_INSTANCE_COUNT) {
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return;
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}
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REG(UART_BASE | UART_DR) = b;
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input_handler[uart] = input;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_isr(void)
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uart_write_byte(uint8_t uart, uint8_t b)
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{
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uint32_t uart_base;
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if(uart >= UART_INSTANCE_COUNT) {
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return;
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}
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uart_base = uart_regs[uart].base;
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/* Block if the TX FIFO is full */
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while(REG(uart_base | UART_FR) & UART_FR_TXFF);
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REG(uart_base | UART_DR) = b;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_isr(uint8_t uart)
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{
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uint32_t uart_base;
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uint16_t mis;
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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uart_base = uart_regs[uart].base;
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/* Store the current MIS and clear all flags early, except the RTM flag.
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* This will clear itself when we read out the entire FIFO contents */
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mis = REG(UART_BASE | UART_MIS) & 0x0000FFFF;
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mis = REG(uart_base | UART_MIS) & 0x0000FFFF;
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REG(UART_BASE | UART_ICR) = 0x0000FFBF;
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REG(uart_base | UART_ICR) = 0x0000FFBF;
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if(mis & (UART_MIS_RXMIS | UART_MIS_RTMIS)) {
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while(!(REG(UART_BASE | UART_FR) & UART_FR_RXFE)) {
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if(input_handler != NULL) {
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||||
input_handler((unsigned char)(REG(UART_BASE | UART_DR) & 0xFF));
|
||||
while(!(REG(uart_base | UART_FR) & UART_FR_RXFE)) {
|
||||
if(input_handler[uart] != NULL) {
|
||||
input_handler[uart]((unsigned char)(REG(uart_base | UART_DR) & 0xFF));
|
||||
} else {
|
||||
/* To prevent an Overrun Error, we need to flush the FIFO even if we
|
||||
* don't have an input_handler. Use mis as a data trash can */
|
||||
mis = REG(UART_BASE | UART_DR);
|
||||
mis = REG(uart_base | UART_DR);
|
||||
}
|
||||
}
|
||||
} else if(mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_FEMIS)) {
|
||||
/* ISR triggered due to some error condition */
|
||||
reset();
|
||||
reset(uart_base);
|
||||
}
|
||||
|
||||
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
#define UART_ISR(u) void uart##u##_isr(void) { uart_isr(u); }
|
||||
UART_ISR(0)
|
||||
UART_ISR(1)
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue