renamed libmc1322x to lib
This commit is contained in:
Mariano Alvira
parent
4a42f24be5
commit
d5b20ddce5
17 changed files with 2 additions and 2 deletions
103
lib/include/crm.h
Normal file
103
lib/include/crm.h
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#ifndef CRM_H
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#define CRM_H
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#include <types.h>
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#define CRM_BASE (0x80003000)
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#define CRM_SYS_CNTL ((volatile uint32_t *) (CRM_BASE+0x00))
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#define CRM_WU_CNTL ((volatile uint32_t *) (CRM_BASE+0x04))
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#define CRM_SLEEP_CNTL ((volatile uint32_t *) (CRM_BASE+0x08))
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#define CRM_BS_CNTL ((volatile uint32_t *) (CRM_BASE+0x0c))
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#define CRM_COP_CNTL ((volatile uint32_t *) (CRM_BASE+0x10))
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#define CRM_COP_SERVICE ((volatile uint32_t *) (CRM_BASE+0x14))
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#define CRM_STATUS ((volatile uint32_t *) (CRM_BASE+0x18))
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#define CRM_MOD_STATUS ((volatile uint32_t *) (CRM_BASE+0x1c))
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#define CRM_WU_COUNT ((volatile uint32_t *) (CRM_BASE+0x20))
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#define CRM_WU_TIMEOUT ((volatile uint32_t *) (CRM_BASE+0x24))
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#define CRM_RTC_COUNT ((volatile uint32_t *) (CRM_BASE+0x28))
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#define CRM_RTC_TIMEOUT ((volatile uint32_t *) (CRM_BASE+0x2c))
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#define CRM_CAL_CNTL ((volatile uint32_t *) (CRM_BASE+0x34))
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#define CRM_CAL_COUNT ((volatile uint32_t *) (CRM_BASE+0x38))
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#define CRM_RINGOSC_CNTL ((volatile uint32_t *) (CRM_BASE+0x3c))
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#define CRM_XTAL_CNTL ((volatile uint32_t *) (CRM_BASE+0x40))
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#define CRM_XTAL32_CNTL ((volatile uint32_t *) (CRM_BASE+0x44))
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#define CRM_VREG_CNTL ((volatile uint32_t *) (CRM_BASE+0x48))
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#define CRM_SW_RST ((volatile uint32_t *) (CRM_BASE+0x50))
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/* CRM_SYS_CNTL bit locations */
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#define XTAL32_EXISTS 5
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/* CRM_WU_CNTL bit locations */
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#define EXT_WU_IEN 20 /* 4 bits */
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#define EXT_WU_EN 4 /* 4 bits */
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#define EXT_WU_EDGE 8 /* 4 bits */
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#define EXT_WU_POL 12 /* 4 bits */
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#define TIMER_WU_EN 0
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#define RTC_WU_EN 1
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#define TIMER_WU_IEN 16
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#define RTC_WU_IEN 17
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/* CRM_STATUS bit locations */
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#define EXT_WU_EVT 4 /* 4 bits, rw1c */
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#define RTC_WU_EVT 3 /* rw1c */
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/* RINGOSC_CNTL bit locations */
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#define ROSC_CTUNE 9 /* 4 bits */
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#define ROSC_FTUNE 4 /* 4 bits */
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#define ROSC_EN 0
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#define ring_osc_on() (set_bit(reg32(CRM_RINGOSC_CNTL),ROSC_EN))
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#define ring_osc_off() (clear_bit(reg32(CRM_RINGOSC_CNTL),ROSC_EN))
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#define REF_OSC 24000000ULL /* reference osc. frequency */
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#define NOMINAL_RING_OSC_SEC 2000 /* nominal ring osc. frequency */
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//extern uint32_t cal_rtc_secs; /* calibrated 2khz rtc seconds */
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/* XTAL32_CNTL bit locations */
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#define XTAL32_GAIN 4 /* 2 bits */
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#define XTAL32_EN 0
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#define xtal32_on() (set_bit(reg32(CRM_XTAL32_CNTL),XTAL32_EN))
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#define xtal32_off() (clear_bit(reg32(CRM_XTAL32_CNTL),XTAL32_EN))
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#define xtal32_exists() (set_bit(reg32(CRM_SYS_CNTL),XTAL32_EXISTS))
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/* enable external wake-ups on kbi 4-7 */
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/* see kbi.h for other kbi specific macros */
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#define enable_ext_wu(kbi) (set_bit(reg32(CRM_WU_CNTL),(EXT_WU_EN+kbi-4)))
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#define disable_ext_wu(kbi) (clear_bit(reg32(CRM_WU_CNTL),(EXT_WU_EN+kbi-4)))
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#define is_ext_wu_evt(kbi) (bit_is_set(reg32(CRM_STATUS),(EXT_WU_EVT+kbi-4)))
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#define clear_ext_wu_evt(kbi) (set_bit(reg32(CRM_STATUS),(EXT_WU_EVT+kbi-4))) /* r1wc bit */
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/* enable wake-up timer */
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#define enable_timer_wu_irq() ((set_bit(reg32(CRM_WU_CNTL),(TIMER_WU_IEN))))
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#define disable_timer_wu_irq() ((clear_bit(reg32(CRM_WU_CNTL),(TIMER_WU_IEN))))
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#define enable_timer_wu() ((set_bit(reg32(CRM_WU_CNTL),(TIMER_WU_EN))))
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#define disable_timer_wu() ((clear_bit(reg32(CRM_WU_CNTL),(TIMER_WU_EN))))
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/* enable wake-up from RTC compare */
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#define enable_rtc_wu_irq() (set_bit(reg32(CRM_WU_CNTL),RTC_WU_IEN))
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#define disable_rtc_wu_irq() (clear_bit(reg32(CRM_WU_CNTL),RTC_WU_IEN))
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#define enable_rtc_wu() ((set_bit(reg32(CRM_WU_CNTL),(RTC_WU_EN))))
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#define disable_rtc_wu() ((clear_bit(reg32(CRM_WU_CNTL),(RTC_WU_EN))))
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#define clear_rtc_wu_evt() (set_bit(reg32(CRM_STATUS),RTC_WU_EVT))
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#define rtc_wu_evt() (bit_is_set(reg32(CRM_STATUS),RTC_WU_EVT))
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#define SLEEP_MODE_HIBERNATE bit(0)
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#define SLEEP_MODE_DOZE bit(1)
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#define SLEEP_PAD_PWR bit(7)
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#define SLEEP_RETAIN_MCU bit(6)
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#define sleep_ram_retain(x) (x<<4) /* 0-3 */
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#define SLEEP_RAM_8K sleep_ram_retain(0)
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#define SLEEP_RAM_32K sleep_ram_retain(1)
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#define SLEEP_RAM_64K sleep_ram_retain(2)
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#define SLEEP_RAM_96K sleep_ram_retain(3)
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#define pack_XTAL_CNTL(ctune4pf, ctune, ftune, ibias) \
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(*CRM_XTAL_CNTL = ((ctune4pf << 25) | (ctune << 21) | ( ftune << 16) | (ibias << 8) | 0x52))
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#endif
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36
lib/include/gpio.h
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36
lib/include/gpio.h
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@ -0,0 +1,36 @@
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#ifndef GPIO_H
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#define GPIO_H
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#define GPIO_PAD_DIR0 ((volatile uint32_t *) 0x80000000)
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#define GPIO_PAD_DIR1 ((volatile uint32_t *) 0x80000004)
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#define GPIO_DATA0 ((volatile uint32_t *) 0x80000008)
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#define GPIO_DATA1 ((volatile uint32_t *) 0x8000000c)
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#define GPIO_PAD_PU_EN0 ((volatile uint32_t *) 0x80000010)
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#define GPIO_PAD_PU_EN1 ((volatile uint32_t *) 0x80000014)
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#define GPIO_FUNC_SEL0 ((volatile uint32_t *) 0x80000018) /* GPIO 15 - 0; 2 bit blocks */
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#define GPIO_FUNC_SEL1 ((volatile uint32_t *) 0x8000001c) /* GPIO 16 - 31; 2 bit blocks */
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#define GPIO_FUNC_SEL2 ((volatile uint32_t *) 0x80000020) /* GPIO 32 - 47; 2 bit blocks */
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#define GPIO_FUNC_SEL3 ((volatile uint32_t *) 0x80000024) /* GPIO 48 - 63; 2 bit blocks */
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#define GPIO_DATA_SEL0 ((volatile uint32_t *) 0x80000028)
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#define GPIO_DATA_SEL1 ((volatile uint32_t *) 0x8000002c)
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#define GPIO_PAD_PU_SEL0 ((volatile uint32_t *) 0x80000030)
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#define GPIO_PAD_PU_SEL1 ((volatile uint32_t *) 0x80000034)
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/* select pullup or pulldown for GPIO 0-31 (b=0-31) */
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#define gpio_sel0_pullup(b) (set_bit(reg32(GPIO_PAD_PU_SEL0),b))
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#define gpio_sel0_pulldown(b) (clear_bit(reg32(GPIO_PAD_PU_SEL0),b))
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/* select pullup or pulldown for GPIO 32-63 (b=32-63) */
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#define gpio_sel1_pullup(b) (set_bit(reg32(GPIO_PAD_PU_SEL1),b-32))
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#define gpio_sel1_pulldown(b) (clear_bit(reg32(GPIO_PAD_PU_SEL1),b-32))
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/* enable/disable pullup for GPIO 0-31 (b=0-31) */
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#define gpio_pu0_enable(b) (set_bit(reg32(GPIO_PAD_PU_EN0),b))
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#define gpio_pu0_disable(b) (clear_bit(reg32(GPIO_PAD_PU_EN0),b))
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/* enable/disable pullup for GPIO 32-63 (b=32-63) */
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#define gpio_pu1_enable(b) (set_bit(reg32(GPIO_PAD_PU_EN1),b-32))
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#define gpio_pu1_disable(b) (clear_bit(reg32(GPIO_PAD_PU_EN1),b-32))
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#endif
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18
lib/include/isr.h
Normal file
18
lib/include/isr.h
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@ -0,0 +1,18 @@
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#ifndef ISR_H
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#define ISR_H
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#define INTBASE (0x80020000)
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#define INTENNUM_OFF (0x8)
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#define INTDISNUM_OFF (0xc)
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#define INTSRC_OFF (0x30)
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#define INTENNUM INTBASE + INTENNUM_OFF
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#define INTDISNUM INTBASE + INTDISNUM_OFF
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#define INTSRC INTBASE + INTSRC_OFF
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#define enable_tmr_irq() *(volatile uint32_t *)(INTENNUM) = 5;
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extern void tmr_isr(void) __attribute__((weak));
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#endif
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421
lib/include/maca.h
Normal file
421
lib/include/maca.h
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#ifndef _MACA_H_
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#define _MACA_H_
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#include <types.h>
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#define MACA_BASE ((volatile uint32_t *) 0x80004000)
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#define MACA_RESET ((volatile uint32_t *) 0x80004004)
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#define MACA_RANDOM ((volatile uint32_t *) 0x80004008)
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#define MACA_CONTROL ((volatile uint32_t *) 0x8000400c)
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#define MACA_STATUS ((volatile uint32_t *) 0x80004010)
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#define MACA_DMARX ((volatile uint32_t *) 0x80004080)
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#define MACA_DMATX ((volatile uint32_t *) 0x80004084)
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#define MACA_GETRXLVL ((volatile uint32_t *) 0x80004098)
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#define MACA_PREAMBLE ((volatile uint32_t *) 0x8000411c)
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#define gMACA_Clock_DIV_c 95
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//rom_base_adr equ 0x00000000 ; rom base address
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//ram_base_adr equ 0x00400000 ; ram base address
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//ram0_base_adr equ 0x00400000 ; ram0 base address (2K words = 8K
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//bytes)
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//ram1_base_adr equ 0x00402000 ; ram1 base address (6K words = 24K
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//bytes)
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//ram2_base_adr equ 0x00408000 ; ram2 base address (8K words = 32K
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//bytes)
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//ram3_base_adr equ 0x00410000 ; ram3 base address (8K words
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enum {
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cc_success = 0,
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cc_timeout = 1,
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cc_channel_busy = 2,
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cc_crc_fail = 3,
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cc_aborted = 4,
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cc_no_ack = 5,
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cc_no_data = 6,
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cc_late_start = 7,
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cc_ext_timeout = 8,
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cc_ext_pnd_timeout = 9,
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cc_nc1 = 10,
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cc_nc2 = 11,
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cc_nc3 = 12,
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cc_cc_external_abort= 13,
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cc_not_completed = 14,
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cc_bus_error = 15
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};
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//control codes for mode bits
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enum {
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control_mode_no_cca = 0,
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control_mode_non_slotted = (1<<3),
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control_mode_slotted = (1<<4)
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};
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//control codes for sequence bits
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enum {
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control_seq_nop = 0,
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control_seq_abort = 1,
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control_seq_wait = 2,
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control_seq_tx = 3,
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control_seq_rx = 4,
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control_seq_txpoll = 5,
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control_seq_cca = 6,
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control_seq_ed = 7
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};
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#define maca_status_cc_mask (0x0F)
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#define maca_reset_rst (1<<0)
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#define maca_reset_cln_on (1<<1)
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#define maca_frmpnd_data_pending (1<<0)
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#define maca_frmpnd_no_data_pending (0x00)
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#define maca_txlen_max_rxlen (127<<16)
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#define max_rx_ackwnd_slotted_mode (0xFFF<<16)
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#define max_rx_ackwnd_normal_mode (0xFFF)
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#define control_pre_count (7<<16) /* preamble reapeat counter */
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#define control_rst_slot (1<<15) /* reset slot counter */
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#define control_role (1<<13) /* set if PAN coordinator */
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#define control_nofc (1<<12) /* set to disable FCS */
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#define control_prm (1<<11) /* set for promiscuous mode */
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#define control_relative (1<<10) /* 1 for relative, 0 for absolute */
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#define control_asap (1<<9) /* 1 start now, 0 timer start */
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#define control_bcn (1<<8) /* 1 beacon only, 0 for a */
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#define control_auto (1<<7) /* 1 continuous rx, rx only once */
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#define control_lfsr (1<<6) /* 1 use polynomial for Turbolink */
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#define maca_irq_strt (1<<15) /*
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STRT
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Bit 15
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Action Started Interrupt—An auto-sequence is started, either
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immediately or by timer trigger.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_sync (1<<14) /*
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SYNC
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Bit 14
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Sync Detected Interrupt—The modem has detected the beginning
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of a new packet
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_cm (1<<13) /*
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CM
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Bit 13
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Complete Clock Interrupt—The complete clock has generated a
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trigger.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_crc (1<<12) /*
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CRC
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Bit 12
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Checksum Failed Interrupt—The checksum failed for the received
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packet.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_flt (1<<11) /*
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FLT
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Bit 11
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Filter Failed Interrupt—The receive header filter failed. 1 = Clear interrupt source
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0 = Leave source untouched
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SFT
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Bit 10
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Soft Complete Clock Interrupt—The soft complete clock has
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generated a trigger.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_sftclk (1<<10)
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#define maca_irq_lvl (1<<9) /*
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LVL
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Bit 9
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FIFO Level interrupt—The receive FIFO level is reached or
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exceeded.
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1 = Clear interrupt source
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0 = Leave source untouched
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Bit 8-5 Reserved bits—Read as zero and written with zero for future
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compatibility. N/A
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*/
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#define maca_irq_rst (1<<4) /*
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RST
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Bit 4
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Reset Interrupt—A non maskable reset interrupt detected (TBD!!!) 1 = Clear interrupt source
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0 = Leave source untouched
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WU
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Bit 3
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Wake-up Interrupt—Low power mode has been exited (TBD in
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connection with CCM module).
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_wu (1<<3)
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#define maca_irq_di (1<<2) /*
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DI
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Bit 2
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Data Indication Interrupt—During receive, a packet has been
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successfully received.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_poll (1<<1) /*
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POLL
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Bit 1
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Poll Indication Interrupt—Issued when data request received (and
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before ACK transmitted). MCU may then set MACA_FRMPND and
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prepare fast response. TBD: Shall this be skipped if
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MACA_FRMPND is clear?
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_acpl (1<<0) /*
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ACPL
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Action Complete Interrupt—Marks the completion of a complete
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auto-sequence.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_start_clk (1<<0)/*
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TMREN & TMRDIS enable/disable start clock
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*/
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#define maca_cpl_clk (1<<1)/*
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TMREN & TMRDIS enable/disable complete clock
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*/
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#define maca_soft_clk (1<<2)/*
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TMREN & TMRDIS enable/disable soft complete clock
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*/
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#define maca_abort_start_clk (1<<3)/*
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TMRDIS abort start clock
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*/
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#define maca_abort_cpl_clk (1<<4)/*
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TMRDIS abort complete clock
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*/
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#define maca_abort_soft_clk (1<<5)/*
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TMRDIS abort soft complete clock
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*/
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#define maca_version (*((volatile uint32_t *)(0x80004000)))
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#define maca_reset (*((volatile uint32_t *)(0x80004004)))
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#define maca_random (*((volatile uint32_t *)(0x80004008)))
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#define maca_control (*((volatile uint32_t *)(0x8000400c)))
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#define maca_status (*((volatile uint32_t *)(0x80004010)))
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#define maca_frmpnd (*((volatile uint32_t *)(0x80004014)))
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#define maca_edvalue (*((volatile uint32_t *)(0x8000401c)))
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#define maca_tmren (*((volatile uint32_t *)(0x80004040)))
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#define maca_tmrdis (*((volatile uint32_t *)(0x80004044)))
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#define maca_clk (*((volatile uint32_t *)(0x80004048)))
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#define maca_startclk (*((volatile uint32_t *)(0x8000404c)))
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#define maca_cplclk (*((volatile uint32_t *)(0x80004050)))
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#define maca_sftclk (*((volatile uint32_t *)(0x80004054)))
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#define maca_clkoffset (*((volatile uint32_t *)(0x80004058)))
|
||||
#define maca_relclk (*((volatile uint32_t *)(0x8000405c)))
|
||||
#define maca_cpltim (*((volatile uint32_t *)(0x80004060)))
|
||||
#define maca_slotoffset (*((volatile uint32_t *)(0x80004064)))
|
||||
#define maca_timestamp (*((volatile uint32_t *)(0x80004068)))
|
||||
#define maca_dmarx (*((volatile uint32_t *)(0x80004080)))
|
||||
#define maca_dmatx (*((volatile uint32_t *)(0x80004084)))
|
||||
#define maca_dmatxpoll (*((volatile uint32_t *)(0x80004088)))
|
||||
#define maca_txlen (*((volatile uint32_t *)(0x8000408c)))
|
||||
#define maca_txseqnr (*((volatile uint32_t *)(0x80004090)))
|
||||
#define maca_setrxlvl (*((volatile uint32_t *)(0x80004094)))
|
||||
#define maca_getrxlvl (*((volatile uint32_t *)(0x80004098)))
|
||||
#define maca_irq (*((volatile uint32_t *)(0x800040c0)))
|
||||
#define maca_clrirq (*((volatile uint32_t *)(0x800040c4)))
|
||||
#define maca_setirq (*((volatile uint32_t *)(0x800040c8)))
|
||||
#define maca_maskirq (*((volatile uint32_t *)(0x800040cc)))
|
||||
#define maca_panid (*((volatile uint32_t *)(0x80004100)))
|
||||
#define maca_addr16 (*((volatile uint32_t *)(0x80004104)))
|
||||
#define maca_maca64hi (*((volatile uint32_t *)(0x80004108)))
|
||||
#define maca_maca64lo (*((volatile uint32_t *)(0x8000410c)))
|
||||
#define maca_fltrej (*((volatile uint32_t *)(0x80004110)))
|
||||
#define maca_divider (*((volatile uint32_t *)(0x80004114)))
|
||||
#define maca_warmup (*((volatile uint32_t *)(0x80004118)))
|
||||
#define maca_preamble (*((volatile uint32_t *)(0x8000411c)))
|
||||
#define maca_whiteseed (*((volatile uint32_t *)(0x80004120)))
|
||||
#define maca_framesync (*((volatile uint32_t *)(0x80004124)))
|
||||
#define maca_framesync2 (*((volatile uint32_t *)(0x80004128)))
|
||||
#define maca_txackdelay (*((volatile uint32_t *)(0x80004140)))
|
||||
#define maca_rxackdelay (*((volatile uint32_t *)(0x80004144)))
|
||||
#define maca_eofdelay (*((volatile uint32_t *)(0x80004148)))
|
||||
#define maca_ccadelay (*((volatile uint32_t *)(0x8000414c)))
|
||||
#define maca_rxend (*((volatile uint32_t *)(0x80004150)))
|
||||
#define maca_txccadelay (*((volatile uint32_t *)(0x80004154)))
|
||||
#define maca_key3 (*((volatile uint32_t *)(0x80004158)))
|
||||
#define maca_key2 (*((volatile uint32_t *)(0x80004158)))
|
||||
#define maca_key1 (*((volatile uint32_t *)(0x80004158)))
|
||||
#define maca_key0 (*((volatile uint32_t *)(0x80004158)))
|
||||
|
||||
|
||||
typedef union maca_version_reg_tag
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t MINOR:8;
|
||||
uint32_t RESERVED1:8;
|
||||
uint32_t MAJOR:8;
|
||||
uint32_t RESERVED2:8;
|
||||
} Bits;
|
||||
uint32_t Reg;
|
||||
} maca_version_reg_t;
|
||||
|
||||
#define maca_version_reg_st ((maca_version_reg_t)(maca_version))
|
||||
|
||||
|
||||
typedef union maca_reset_reg_tag
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t RESERVED:30;
|
||||
uint32_t CLK_ON:1;
|
||||
uint32_t RST:1;
|
||||
} Bits;
|
||||
uint32_t Reg;
|
||||
} maca_reset_reg_t;
|
||||
|
||||
#define maca_reset_reg_st ((maca_reset_reg_t)(maca_reset))
|
||||
|
||||
|
||||
typedef union maca_ctrl_reg_tag
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t RESERVED:11;
|
||||
uint32_t ISM:1;
|
||||
uint32_t PRE_COUNT:4;
|
||||
uint32_t RSTO:1;
|
||||
uint32_t RSV:1;
|
||||
uint32_t ROLE:1;
|
||||
uint32_t NOFC:1;
|
||||
uint32_t PRM:1;
|
||||
uint32_t rel:1;
|
||||
uint32_t ASAP:1;
|
||||
uint32_t BCN:1;
|
||||
uint32_t AUTO:1;
|
||||
uint32_t LFSR:1;
|
||||
uint32_t TM:1;
|
||||
uint32_t MODE:2;
|
||||
uint32_t SEQUENCE:3;
|
||||
} Bits;
|
||||
uint32_t Reg;
|
||||
} maca_ctrl_reg_t;
|
||||
|
||||
#define maca_control_ism (1<<20)
|
||||
#define maca_control_zigbee (~maca_control_ism)
|
||||
|
||||
#define maca_ctrl_reg_st ((maca_ctrl_reg_t *)(&maca_reset))
|
||||
#define _set_maca_test_mode(x) (maca_ctrl_reg_st->Bits.TM = x)
|
||||
#define _set_maca_sequence(x) (maca_ctrl_reg_st->Bits.SEQUENCE = x)
|
||||
#define _set_maca_asap(x) (maca_ctrl_reg_st->Bits.ASAP = x)
|
||||
|
||||
|
||||
#define MACA_CTRL_ZIGBEE_MODE (0)
|
||||
#define MACA_CTRL_ISM_MODE (1)
|
||||
#define MACA_CTRL_PRM_NORMAL_MODE (0)
|
||||
#define MACA_CTRL_PRM_PROMISCUOUS_MODE (1)
|
||||
#define MACA_CTRL_BCN_ALL (0)
|
||||
#define MACA_CTRL_BCN_BEACON (1)
|
||||
#define MACA_CTRL_TM_NORMAL (0)
|
||||
#define MACA_CTRL_TM_TEST (1)
|
||||
#define MACA_CTRL_MODE_NO_CCA (0)
|
||||
#define MACA_CTRL_MODE_NON_SLOTTED (1)
|
||||
#define MACA_CTRL_MODE_SLOTTED (2)
|
||||
|
||||
|
||||
typedef union maca_status_reg_tag
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t RESERVED:16;
|
||||
uint32_t TO:1;
|
||||
uint32_t CRC:1;
|
||||
uint32_t BUSY:1;
|
||||
uint32_t OVR:1;
|
||||
uint32_t zigbee:1;
|
||||
uint32_t :7;
|
||||
uint32_t COMPLETE_CODE:4;
|
||||
} Bits;
|
||||
uint32_t Reg;
|
||||
} maca_status_reg_t;
|
||||
|
||||
|
||||
typedef enum maca_freq_chann_tag
|
||||
{
|
||||
SMAC_CHANN_11 = 0,
|
||||
SMAC_CHANN_12,
|
||||
SMAC_CHANN_13,
|
||||
SMAC_CHANN_14,
|
||||
SMAC_CHANN_15,
|
||||
SMAC_CHANN_16,
|
||||
SMAC_CHANN_17,
|
||||
SMAC_CHANN_18,
|
||||
SMAC_CHANN_19,
|
||||
SMAC_CHANN_20,
|
||||
SMAC_CHANN_21,
|
||||
SMAC_CHANN_22,
|
||||
SMAC_CHANN_23,
|
||||
SMAC_CHANN_24,
|
||||
SMAC_CHANN_25,
|
||||
SMAC_CHANN_26,
|
||||
MAX_SMAC_CHANNELS
|
||||
} maca_freq_chann_t;
|
||||
|
||||
|
||||
typedef union maca_maskirq_reg_tag
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t RESERVED1:16;
|
||||
uint32_t STRT:1;
|
||||
uint32_t SYNC:1;
|
||||
uint32_t CM:1;
|
||||
uint32_t CRC:1;
|
||||
uint32_t FLT:1;
|
||||
uint32_t SFT:1;
|
||||
uint32_t LVL:1;
|
||||
uint32_t RESERVED0:4;
|
||||
uint32_t NOT_USED1:1;
|
||||
uint32_t NOT_USED0:1;
|
||||
uint32_t DI:1;
|
||||
uint32_t POLL:1;
|
||||
uint32_t ACPL:1;
|
||||
} Bits;
|
||||
uint32_t Reg;
|
||||
} maca_maskirq_reg_t;
|
||||
|
||||
|
||||
#define _is_action_complete_interrupt(x) (0 != (maca_irq_acpl & x))
|
||||
#define _is_filter_failed_interrupt(x) (0 != (maca_irq_flt & x))
|
||||
#define _is_checksum_failed_interrupt(x) (0 != (maca_irq_crc & x))
|
||||
|
||||
#define SMAC_MACA_CNTL_INIT_STATE ( control_prm | control_nofc | control_mode_non_slotted )
|
||||
|
||||
#define MACA_WRITE(reg, src) (reg = src)
|
||||
#define MACA_READ(reg) reg
|
||||
|
||||
void reset_maca(void);
|
||||
void init_phy(void);
|
||||
void flyback_init(void);
|
||||
void ResumeMACASync(void);
|
||||
void radio_init(void);
|
||||
void radio_off(void);
|
||||
void radio_on(void);
|
||||
uint32_t init_from_flash(uint32_t addr);
|
||||
void set_power(uint8_t power);
|
||||
void set_channel(uint8_t chan);
|
||||
|
||||
#endif // _MACA_H_
|
||||
16
lib/include/mc1322x.h
Normal file
16
lib/include/mc1322x.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#ifndef MC1322X_H
|
||||
#define MC1322X_H
|
||||
|
||||
#include "types.h"
|
||||
#include "isr.h"
|
||||
#include "gpio.h"
|
||||
#include "crm.h"
|
||||
#include "nvm.h"
|
||||
#include "tmr.h"
|
||||
#include "maca.h"
|
||||
#include "uart1.h"
|
||||
#include "utils.h"
|
||||
|
||||
#include "put.h" /* this is a temp. lib */
|
||||
|
||||
#endif
|
||||
47
lib/include/nvm.h
Normal file
47
lib/include/nvm.h
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
#ifndef NVM_H
|
||||
#define NVM_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
gNvmType_NoNvm_c,
|
||||
gNvmType_SST_c,
|
||||
gNvmType_ST_c,
|
||||
gNvmType_ATM_c,
|
||||
gNvmType_Max_c
|
||||
} nvmType_t;
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
gNvmErrNoError_c = 0,
|
||||
gNvmErrInvalidInterface_c,
|
||||
gNvmErrInvalidNvmType_c,
|
||||
gNvmErrInvalidPointer_c,
|
||||
gNvmErrWriteProtect_c,
|
||||
gNvmErrVerifyError_c,
|
||||
gNvmErrAddressSpaceOverflow_c,
|
||||
gNvmErrBlankCheckError_c,
|
||||
gNvmErrRestrictedArea_c,
|
||||
gNvmErrMaxError_c
|
||||
} nvmErr_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
gNvmInternalInterface_c,
|
||||
gNvmExternalInterface_c,
|
||||
gNvmInterfaceMax_c
|
||||
} nvmInterface_t;
|
||||
|
||||
/* ROM code seems to be THUMB */
|
||||
/* need to be in a THUMB block before calling them */
|
||||
extern nvmErr_t (*nvm_detect)(nvmInterface_t nvmInterface,nvmType_t* pNvmType);
|
||||
extern nvmErr_t (*nvm_read)(nvmInterface_t nvmInterface , nvmType_t nvmType , void *pDest, uint32_t address, uint32_t numBytes);
|
||||
extern nvmErr_t (*nvm_write)(nvmInterface_t nvmInterface, nvmType_t nvmType ,void *pSrc, uint32_t address, uint32_t numBytes);
|
||||
/* sector bit field selects which sector to erase */
|
||||
/* SST flash has 32 sectors 4096 bytes each */
|
||||
/* bit 0 is the first sector, bit 31 is the last */
|
||||
extern nvmErr_t (*nvm_erase)(nvmInterface_t nvmInterface, nvmType_t nvmType ,uint32_t sectorBitfield);
|
||||
extern void(*nvm_setsvar)(uint32_t zero_for_awesome);
|
||||
#endif //NVM_H
|
||||
10
lib/include/put.h
Normal file
10
lib/include/put.h
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#ifndef PUT_H
|
||||
#define PUT_H
|
||||
|
||||
void putchr(char c);
|
||||
void putstr(char *s);
|
||||
void put_hex(uint8_t x);
|
||||
void put_hex16(uint16_t x);
|
||||
void put_hex32(uint32_t x);
|
||||
|
||||
#endif
|
||||
92
lib/include/tmr.h
Normal file
92
lib/include/tmr.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
#include "utils.h"
|
||||
|
||||
/* Timer registers are all 16-bit wide with 16-bit access only */
|
||||
#define TMR_OFFSET (0x20)
|
||||
#define TMR_BASE (0x80007000)
|
||||
#define TMR0_BASE (TMR_BASE)
|
||||
#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
|
||||
#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
|
||||
#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
|
||||
|
||||
#define TMR_REGOFF_COMP1 (0x0)
|
||||
#define TMR_REGOFF_COMP2 (0x2)
|
||||
#define TMR_REGOFF_CAPT (0x4)
|
||||
#define TMR_REGOFF_LOAD (0x6)
|
||||
#define TMR_REGOFF_HOLD (0x8)
|
||||
#define TMR_REGOFF_CNTR (0xa)
|
||||
#define TMR_REGOFF_CTRL (0xc)
|
||||
#define TMR_REGOFF_SCTRL (0xe)
|
||||
#define TMR_REGOFF_CMPLD1 (0x10)
|
||||
#define TMR_REGOFF_CMPLD2 (0x12)
|
||||
#define TMR_REGOFF_CSCTRL (0x14)
|
||||
#define TMR_REGOFF_ENBL (0x1e)
|
||||
|
||||
/* one enable register to rule them all */
|
||||
#define TMR_ENBL ((volatile uint16_t *) TMR0_BASE + TMR_REGOFF_ENBL)
|
||||
|
||||
/* Timer 0 registers */
|
||||
#define TMR0_COMP1 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP1))
|
||||
#define TMR0_COMP_UP TMR0_COMP1
|
||||
#define TMR0_COMP2 (TMR0_BASE + TMR_REGOFF_COMP2)
|
||||
#define TMR0_COMP_DOWN TMR0_COMP2
|
||||
#define TMR0_CAPT ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CAPT))
|
||||
#define TMR0_LOAD ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_LOAD))
|
||||
#define TMR0_HOLD ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_HOLD))
|
||||
#define TMR0_CNTR ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CTRL))
|
||||
#define TMR0_CTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CTRL))
|
||||
#define TMR0_SCTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_SCTRL))
|
||||
#define TMR0_CMPLD1 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD1))
|
||||
#define TMR0_CMPLD2 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD2))
|
||||
#define TMR0_CSCTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CSCTRL))
|
||||
|
||||
/* Timer 1 registers */
|
||||
#define TMR1_COMP1 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP1))
|
||||
#define TMR1_COMP_UP TMR1_COMP1
|
||||
#define TMR1_COMP2 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP2))
|
||||
#define TMR1_COMP_DOWN TMR1_COMP2
|
||||
#define TMR1_CAPT ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CAPT))
|
||||
#define TMR1_LOAD ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_LOAD))
|
||||
#define TMR1_HOLD ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_HOLD))
|
||||
#define TMR1_CNTR ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CTRL))
|
||||
#define TMR1_CTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CTRL))
|
||||
#define TMR1_SCTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_SCTRL))
|
||||
#define TMR1_CMPLD1 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD1))
|
||||
#define TMR1_CMPLD2 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD2))
|
||||
#define TMR1_CSCTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CSCTRL))
|
||||
|
||||
/* Timer 2 registers */
|
||||
#define TMR2_COMP1 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP1))
|
||||
#define TMR2_COMP_UP TMR2_COMP1
|
||||
#define TMR2_COMP2 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP2))
|
||||
#define TMR2_COMP_DOWN TMR2_COMP2
|
||||
#define TMR2_CAPT ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CAPT))
|
||||
#define TMR2_LOAD ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_LOAD))
|
||||
#define TMR2_HOLD ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_HOLD))
|
||||
#define TMR2_CNTR ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CTRL))
|
||||
#define TMR2_CTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CTRL))
|
||||
#define TMR2_SCTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_SCTRL))
|
||||
#define TMR2_CMPLD1 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD1))
|
||||
#define TMR2_CMPLD2 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD2))
|
||||
#define TMR2_CSCTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CSCTRL))
|
||||
|
||||
/* Timer 3 registers */
|
||||
#define TMR3_COMP1 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP1))
|
||||
#define TMR3_COMP_UP TMR3_COMP1
|
||||
#define TMR3_COMP2 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP2))
|
||||
#define TMR3_COMP_DOWN TMR3_COMP2
|
||||
#define TMR3_CAPT ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CAPT))
|
||||
#define TMR3_LOAD ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_LOAD))
|
||||
#define TMR3_HOLD ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_HOLD))
|
||||
#define TMR3_CNTR ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CTRL))
|
||||
#define TMR3_CTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CTRL))
|
||||
#define TMR3_SCTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_SCTRL))
|
||||
#define TMR3_CMPLD1 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD1))
|
||||
#define TMR3_CMPLD2 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD2))
|
||||
#define TMR3_CSCTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CSCTRL))
|
||||
|
||||
#define TCF 15
|
||||
#define TCF1 4
|
||||
#define TCF2 5
|
||||
|
||||
#define TMR(num, reg) CAT2(TMR,num,_##reg)
|
||||
|
||||
13
lib/include/types.h
Normal file
13
lib/include/types.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#ifndef _TYPES_H
|
||||
#define _TYPES_H
|
||||
|
||||
typedef signed char int8_t;
|
||||
typedef unsigned char uint8_t;
|
||||
typedef signed short int16_t;
|
||||
typedef unsigned short uint16_t;
|
||||
typedef signed long int32_t;
|
||||
typedef unsigned long uint32_t;
|
||||
typedef signed long long int64_t;
|
||||
typedef unsigned long long uint64_t;
|
||||
|
||||
#endif
|
||||
16
lib/include/uart1.h
Normal file
16
lib/include/uart1.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#ifndef UART1_H
|
||||
#define UART1_H
|
||||
|
||||
#define UART1_CON ((volatile uint32_t *) 0x80005000)
|
||||
#define UART1_STAT ((volatile uint32_t *) 0x80005004)
|
||||
#define UART1_DATA ((volatile uint32_t *) 0x80005008)
|
||||
#define UR1CON ((volatile uint32_t *) 0x8000500c)
|
||||
#define UT1CON ((volatile uint32_t *) 0x80005010)
|
||||
#define UART1_CTS ((volatile uint32_t *) 0x80005014)
|
||||
#define UART1_BR ((volatile uint32_t *) 0x80005018)
|
||||
|
||||
int uart1_putchar(int c);
|
||||
|
||||
#define uart1_can_get() (*UR1CON > 0)
|
||||
|
||||
#endif
|
||||
14
lib/include/utils.h
Normal file
14
lib/include/utils.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef UTILS_H
|
||||
#define UTILS_H
|
||||
|
||||
#define mem32(x) ((volatile uint32_t *)(x))
|
||||
#define mem16(x) ((volatile uint16_t *)(x))
|
||||
|
||||
#define CAT2(x, y, z) x##y##z
|
||||
|
||||
#define bit(bit) (1 << bit)
|
||||
#define bit_is_set(val, bit) (((val & (1 << bit)) >> bit) == 1)
|
||||
#define clear_bit(val, bit) (val = (val & ~(1 << bit)))
|
||||
#define set_bit(val, bit) (val = (val | (1 << bit)))
|
||||
|
||||
#endif /* UTILS_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue