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tmr-ints

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This commit is contained in:
Mariano Alvira 2010-02-26 16:15:26 -05:00
parent cd5e5b1706
commit d3fed95235
3 changed files with 21 additions and 86 deletions
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6
src/isr.c
View file

@ -1,7 +1,5 @@
#include "types.h" #include <mc1322x.h>
#include "isr.h" #include <types.h>
#define reg32(x) (*(volatile uint32_t *)(x))
__attribute__ ((section (".irq"))) __attribute__ ((section (".irq")))
__attribute__ ((interrupt("IRQ"))) __attribute__ ((interrupt("IRQ")))

2
tests/Makefile
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@ -6,7 +6,7 @@ MC1322X := ..
COBJS := tests.o put.o COBJS := tests.o put.o
# all of the target programs to build # all of the target programs to build
TARGETS := blink-red blink-green blink-blue blink-white blink-allio uart1-loopback nvm-read nvm-write romimg flasher tmr TARGETS := blink-red blink-green blink-blue blink-white blink-allio uart1-loopback nvm-read nvm-write romimg flasher tmr tmr-ints
include $(MC1322X)/Makefile.include include $(MC1322X)/Makefile.include

99
tests/tmr-ints.c
View file

@ -1,63 +1,15 @@
/* Timer registers are all 16-bit wide with 16-bit access only */ #include <mc1322x.h>
#define TMR_OFFSET (0x20) #include <board.h>
#define TMR_BASE (0x80007000)
#define TMR0_BASE (TMR_BASE)
#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
#define TMR_REGOFF_COMP1 (0x0) #include "tests.h"
#define TMR_REGOFF_COMP2 (0x2) #include "config.h"
#define TMR_REGOFF_CAPT (0x4)
#define TMR_REGOFF_LOAD (0x6)
#define TMR_REGOFF_HOLD (0x8)
#define TMR_REGOFF_CNTR (0xa)
#define TMR_REGOFF_CTRL (0xc)
#define TMR_REGOFF_SCTRL (0xe)
#define TMR_REGOFF_CMPLD1 (0x10)
#define TMR_REGOFF_CMPLD2 (0x12)
#define TMR_REGOFF_CSCTRL (0x14)
#define TMR_REGOFF_ENBL (0x1e)
/* Timer 0 registers */
#define TMR0_COMP1 (TMR0_BASE + TMR_REGOFF_COMP1)
#define TMR0_COMP_UP TMR0_COMP1
#define TMR0_COMP2 (TMR0_BASE + TMR_REGOFF_COMP2)
#define TMR0_COMP_DOWN TMR0_COMP2
#define TMR0_CAPT (TMR0_BASE + TMR_REGOFF_CAPT)
#define TMR0_LOAD (TMR0_BASE + TMR_REGOFF_LOAD)
#define TMR0_HOLD (TMR0_BASE + TMR_REGOFF_HOLD)
#define TMR0_CNTR (TMR0_BASE + TMR_REGOFF_CTRL)
#define TMR0_CTRL (TMR0_BASE + TMR_REGOFF_CTRL)
#define TMR0_SCTRL (TMR0_BASE + TMR_REGOFF_SCTRL)
#define TMR0_CMPLD1 (TMR0_BASE + TMR_REGOFF_CMPLD1)
#define TMR0_CMPLD2 (TMR0_BASE + TMR_REGOFF_CMPLD2)
#define TMR0_CSCTRL (TMR0_BASE + TMR_REGOFF_CSCTRL)
/* one enable register to rule them all */
#define TMR_ENBL TMR0_BASE + TMR_REGOFF_ENBL
#define MBAR_GPIO 0x80000000
#define GPIO_PAD_DIR0 0x80000000
#define GPIO_DATA0 0x80000008
#define UART1_DATA 0x80005008
#define DELAY 400000
#define reg32(x) (*(volatile uint32_t *)(x))
#define reg16(x) (*(volatile uint16_t *)(x))
#include "embedded_types.h"
//#include "sys-interrupt.h"
#include "isr.h"
#include "led.h"
volatile uint8_t led; volatile uint8_t led;
#define LED_VAL LED_PURPLE #define LED_VAL LED_PURPLE
#define led_init() do { reg32(GPIO_PAD_DIR0) = LED_VAL; } while(0); #define led_init() do { *GPIO_PAD_DIR0 = LED_VAL; } while(0);
#define led_on() do { led = 1; reg32(GPIO_DATA0) = LED_VAL; } while(0); #define led_on() do { led = 1; *GPIO_DATA0 = LED_VAL; } while(0);
#define led_off() do { led = 0; reg32(GPIO_DATA0) = 0x00000000; } while(0); #define led_off() do { led = 0; *GPIO_DATA0 = 0x00000000; } while(0);
void toggle_led(void) { void toggle_led(void) {
if(0 == led) { if(0 == led) {
@ -72,27 +24,14 @@ void toggle_led(void) {
void tmr_isr(void) { void tmr_isr(void) {
toggle_led(); toggle_led();
reg16(TMR0_SCTRL) = 0; *TMR0_SCTRL = 0;
reg16(TMR0_CSCTRL) = 0x0040; /* clear compare flag */ *TMR0_CSCTRL = 0x0040; /* clear compare flag */
} }
/* void enIRQ(void) { */
/* asm volatile ( */
/* ".code 32;" */
/* "msr cpsr_c,#0x10;" */
/* ".code 16;" */
/* ); */
/* } */
__attribute__ ((section ("startup")))
void main(void) { void main(void) {
// *(volatile uint32_t *)0x80020010 = 0x20;
// *(volatile uint32_t *)0x80020034 = 0xffff; //force an int.
/* pin direction */ /* pin direction */
led_init(); led_init();
@ -107,22 +46,20 @@ void main(void) {
#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */ #define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
#define OUT_MODE 0 /* OFLAG is asserted while counter is active */ #define OUT_MODE 0 /* OFLAG is asserted while counter is active */
reg16(TMR_ENBL) = 0; /* tmrs reset to enabled */ *TMR_ENBL = 0; /* tmrs reset to enabled */
reg16(TMR0_SCTRL) = 0; *TMR0_SCTRL = 0;
reg16(TMR0_CSCTRL) =0x0040; *TMR0_CSCTRL = 0x0040;
reg16(TMR0_LOAD) = 0; /* reload to zero */ *TMR0_LOAD = 0; /* reload to zero */
reg16(TMR0_COMP_UP) = 18750; /* trigger a reload at the end */ *TMR0_COMP_UP = 18750; /* trigger a reload at the end */
reg16(TMR0_CMPLD1) = 18750; /* compare 1 triggered reload level, 10HZ maybe? */ *TMR0_CMPLD1 = 18750; /* compare 1 triggered reload level, 10HZ maybe? */
reg16(TMR0_CNTR) = 0; /* reset count register */ *TMR0_CNTR = 0; /* reset count register */
reg16(TMR0_CTRL) = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE); *TMR0_CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
reg16(TMR_ENBL) = 0xf; /* enable all the timers --- why not? */ *TMR_ENBL = 0xf; /* enable all the timers --- why not? */
led_on(); led_on();
enable_tmr_irq(); enable_tmr_irq();
// enIRQ();
/* go into user mode to handle IRQs */ /* go into user mode to handle IRQs */
/* disabling interrupts is now difficult */ /* disabling interrupts is now difficult */
asm(".code 32;" asm(".code 32;"