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Adding support for AtMega128RFR2 and AtMega256RFR2

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This commit is contained in:
Robert Olsson 2016-02-22 20:14:06 +01:00
parent 93b9089164
commit d3980668ee
9 changed files with 478 additions and 30 deletions
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2
cpu/avr/dev/clock-avr.h
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@ -73,7 +73,7 @@
TIMSK0 = _BV (OCIE0A); TIMSK0 = _BV (OCIE0A);
#elif defined (__AVR_ATmega1284P__) || (__AVR_AT90USB1287__) || (__AVR_ATmega1281__) || defined (__AVR_ATmega128RFA1__) #elif defined (__AVR_ATmega1284P__) || (__AVR_AT90USB1287__) || (__AVR_ATmega1281__) || defined (__AVR_ATmega128RFA1__) || defined (__AVR_ATmega128RFR2__) || defined (__AVR_ATmega256RFR2__)
/* /*
The Raven has a 32768Hz watch crystal that can be used to clock the timer The Raven has a 32768Hz watch crystal that can be used to clock the timer
while the 1284p is sleeping. The Jackdaw has pads for a crystal. The crystal while the 1284p is sleeping. The Jackdaw has pads for a crystal. The crystal

2
cpu/avr/dev/rs232.c
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@ -83,7 +83,7 @@
#define NUMPORTS RS232_CONF_NUMPORTS #define NUMPORTS RS232_CONF_NUMPORTS
#endif #endif
#if defined (__AVR_ATmega128__) || defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega1281__) || defined(__AVR_ATmega128RFA1__) #if defined (__AVR_ATmega128__) || defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega1281__) || defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
#ifndef NUMPORTS #ifndef NUMPORTS
#define NUMPORTS 2 #define NUMPORTS 2
#elif NUMPORTS > 2 #elif NUMPORTS > 2

4
cpu/avr/dev/rs232.h
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@ -49,6 +49,10 @@
#include "dev/rs232_at90usb1287.h" #include "dev/rs232_at90usb1287.h"
#elif defined (__AVR_ATmega128RFA1__) #elif defined (__AVR_ATmega128RFA1__)
#include "dev/rs232_atmega128rfa1.h" #include "dev/rs232_atmega128rfa1.h"
#elif defined (__AVR_ATmega128RFR2__)
#include "dev/rs232_atmega128rfa1.h"
#elif defined (__AVR_ATmega256RFR2__)
#include "dev/rs232_atmega128rfa1.h"
#elif defined (__AVR_ATmega644__) || defined (__AVR_ATmega328P__) #elif defined (__AVR_ATmega644__) || defined (__AVR_ATmega328P__)
#include "dev/rs232_atmega644.h" #include "dev/rs232_atmega644.h"
#elif defined (__AVR_ATmega8__) || defined (__AVR_ATmega8515__) \ #elif defined (__AVR_ATmega8__) || defined (__AVR_ATmega8515__) \

398
cpu/avr/radio/rf230bb/atmega256rfr2_registermap.h Normal file
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@ -0,0 +1,398 @@
/**
* @file
* @brief This file contains RF230-formatted register definitions for the atmega128rfa1
*/
/* Copyright (c) 2008, Swedish Institute of Computer Science
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef PHY256RFR2_REGISTERMAP_EXTERNAL_H
#define PHY256RFR2_REGISTERMAP_EXTERNAL_H
/* RF230 register access is through SPI which transfers 8 bits address/8 bits data.
* ATmega128rfa1 registers are defined in I/O space, e.g. in gcc /include/avr/iom128rfa1.h
* A typical definition is #define TRX_STATUS _SFR_MEM8(0x141)
* Registers can be read with a macro, but the args for subregisters don't expand properly so the actual address
* is used with explicit _SFR_MEM8 in the subregister read/write routines.
*/
#define RG_TRX_STATUS TRX_STATUS
#define SR_TRX_STATUS 0x141, 0x1f, 0
#define SR_TRX_CMD 0x142, 0x1f, 0
#define STATE_TRANSITION (31)
#define SR_TX_PWR 0x145, 0x0f, 0
#define RG_VERSION_NUM VERSION_NUM
#define RG_MAN_ID_0 MAN_ID_0
#define RG_IRQ_MASK IRQ_MASK
#define SR_MAX_FRAME_RETRIES 0x16C, 0xf0, 4
#define SR_TX_AUTO_CRC_ON 0x144, 0x20, 5
#define SR_TRAC_STATUS 0x142, 0xe0, 5
#define SR_CHANNEL 0x148, 0x1f, 0
#define SR_CCA_MODE 0x148, 0x60, 5
#define SR_CCA_REQUEST 0x148, 0x80, 7
#define RG_PAN_ID_0 PAN_ID_0
#define RG_PAN_ID_1 PAN_ID_1
#define RG_SHORT_ADDR_0 SHORT_ADDR_0
#define RG_SHORT_ADDR_1 SHORT_ADDR_1
#define RG_IEEE_ADDR_0 IEEE_ADDR_0
#define RG_IEEE_ADDR_1 IEEE_ADDR_1
#define RG_IEEE_ADDR_2 IEEE_ADDR_2
#define RG_IEEE_ADDR_3 IEEE_ADDR_3
#define RG_IEEE_ADDR_4 IEEE_ADDR_4
#define RG_IEEE_ADDR_5 IEEE_ADDR_5
#define RG_IEEE_ADDR_6 IEEE_ADDR_6
#define RG_IEEE_ADDR_7 IEEE_ADDR_7
//#define SR_ED_LEVEL 0x147, 0xff, 0
#define RG_PHY_ED_LEVEL PHY_ED_LEVEL
#define RG_RX_SYN RX_SYN
#define SR_RSSI 0x146, 0x1f, 0
#define SR_RX_SYN 0x155, 0xff, 0
#define SR_TRX_RPC 0x156, 0xff, 0
#define SR_XAH_CTRL_1 0x157, 0xf5, 2
#define SR_PLL_CF_START 0x15a, 0x80, 7
#define SR_PLL_DCU_START 0x15b, 0x80, 7
#define SR_MAX_CSMA_RETRIES 0x16c, 0x0e, 1
#define RG_CSMA_BE CSMA_BE
#define RG_CSMA_SEED_0 CSMA_SEED_0
#define RG_PHY_RSSI PHY_RSSI
//#define SR_CCA_CS_THRES 0x149, 0xf0, 4
#define SR_CCA_ED_THRES 0x149, 0x0f, 0
#define SR_CCA_DONE 0x141, 0x80, 7
#define SR_CCA_STATUS 0x141, 0x40, 6
#define SR_AACK_SET_PD 0x16e, 0x20, 5
#define SR_CSMA_SEED_1 0x16e, 0x10, 4
/* RF230 register assignments, for reference */
#if 1
//#define HAVE_REGISTER_MAP (1)
/** Offset for register TRX_STATUS */
//#define RG_TRX_STATUS (0x01)
/** Access parameters for sub-register CCA_DONE in register @ref RG_TRX_STATUS */
//#define SR_CCA_DONE 0x01, 0x80, 7
/** Access parameters for sub-register CCA_STATUS in register @ref RG_TRX_STATUS */
//#define SR_CCA_STATUS 0x01, 0x40, 6
//#define SR_reserved_01_3 0x01, 0x20, 5
/** Access parameters for sub-register TRX_STATUS in register @ref RG_TRX_STATUS */
//#define SR_TRX_STATUS 0x01, 0x1f, 0
/** Constant P_ON for sub-register @ref SR_TRX_STATUS */
//#define P_ON (0)
/** Constant BUSY_RX for sub-register @ref SR_TRX_STATUS */
#define BUSY_RX (1)
/** Constant BUSY_TX for sub-register @ref SR_TRX_STATUS */
#define BUSY_TX (2)
/** Constant RX_ON for sub-register @ref SR_TRX_STATUS */
#define RX_ON (6)
/** Constant TRX_OFF for sub-register @ref SR_TRX_STATUS */
#define TRX_OFF (8)
/** Constant PLL_ON for sub-register @ref SR_TRX_STATUS */
#define PLL_ON (9)
/** Constant SLEEP for sub-register @ref SR_TRX_STATUS */
//#define SLEEP (15)
/** Constant BUSY_RX_AACK for sub-register @ref SR_TRX_STATUS */
#define BUSY_RX_AACK (17)
/** Constant BUSY_TX_ARET for sub-register @ref SR_TRX_STATUS */
#define BUSY_TX_ARET (18)
/** Constant RX_AACK_ON for sub-register @ref SR_TRX_STATUS */
#define RX_AACK_ON (22)
/** Constant TX_ARET_ON for sub-register @ref SR_TRX_STATUS */
#define TX_ARET_ON (25)
/** Constant RX_ON_NOCLK for sub-register @ref SR_TRX_STATUS */
//#define RX_ON_NOCLK (28)
/** Constant RX_AACK_ON_NOCLK for sub-register @ref SR_TRX_STATUS */
//#define RX_AACK_ON_NOCLK (29)
/** Constant BUSY_RX_AACK_NOCLK for sub-register @ref SR_TRX_STATUS */
//#define BUSY_RX_AACK_NOCLK (30)
/** Constant STATE_TRANSITION for sub-register @ref SR_TRX_STATUS */
//#define STATE_TRANSITION (31)
/** Offset for register TRX_STATE */
//#define RG_TRX_STATE (0x02)
/** Access parameters for sub-register TRAC_STATUS in register @ref RG_TRX_STATE */
//#define SR_TRAC_STATUS 0x02, 0xe0, 5
/** Access parameters for sub-register TRX_CMD in register @ref RG_TRX_STATE */
//#define SR_TRX_CMD 0x02, 0x1f, 0
/** Constant CMD_NOP for sub-register @ref SR_TRX_CMD */
//#define CMD_NOP (0)
/** Constant CMD_TX_START for sub-register @ref SR_TRX_CMD */
//#define CMD_TX_START (2)
/** Constant CMD_FORCE_TRX_OFF for sub-register @ref SR_TRX_CMD */
#define CMD_FORCE_TRX_OFF (3)
///** Constant CMD_RX_ON for sub-register @ref SR_TRX_CMD */
//#define CMD_RX_ON (6)
///** Constant CMD_TRX_OFF for sub-register @ref SR_TRX_CMD */
//#define CMD_TRX_OFF (8)
///** Constant CMD_PLL_ON for sub-register @ref SR_TRX_CMD */
//#define CMD_PLL_ON (9)
///** Constant CMD_RX_AACK_ON for sub-register @ref SR_TRX_CMD */
//#define CMD_RX_AACK_ON (22)
///** Constant CMD_TX_ARET_ON for sub-register @ref SR_TRX_CMD */
//#define CMD_TX_ARET_ON (25)
///** Offset for register TRX_CTRL_0 */
//#define RG_TRX_CTRL_0 (0x03)
///** Offset for register TRX_CTRL_1 */
//#define RG_TRX_CTRL_1 (0x04)
///** Access parameters for sub-register PAD_IO in register @ref RG_TRX_CTRL_0 */
//#define SR_PAD_IO 0x03, 0xc0, 6
///** Access parameters for sub-register PAD_IO_CLKM in register @ref RG_TRX_CTRL_0 */
//#define SR_PAD_IO_CLKM 0x03, 0x30, 4
///** Constant CLKM_2mA for sub-register @ref SR_PAD_IO_CLKM */
//#define CLKM_2mA (0)
///** Constant CLKM_4mA for sub-register @ref SR_PAD_IO_CLKM */
//#define CLKM_4mA (1)
///** Constant CLKM_6mA for sub-register @ref SR_PAD_IO_CLKM */
//#define CLKM_6mA (2)
///** Constant CLKM_8mA for sub-register @ref SR_PAD_IO_CLKM */
//#define CLKM_8mA (3)
///** Access parameters for sub-register CLKM_SHA_SEL in register @ref RG_TRX_CTRL_0 */
//#define SR_CLKM_SHA_SEL 0x03, 0x08, 3
///** Access parameters for sub-register CLKM_CTRL in register @ref RG_TRX_CTRL_0 */
//#define SR_CLKM_CTRL 0x03, 0x07, 0
///** Constant CLKM_no_clock for sub-register @ref SR_CLKM_CTRL */
//#define CLKM_no_clock (0)
///** Constant CLKM_1MHz for sub-register @ref SR_CLKM_CTRL */
//#define CLKM_1MHz (1)
///** Constant CLKM_2MHz for sub-register @ref SR_CLKM_CTRL */
//#define CLKM_2MHz (2)
///** Constant CLKM_4MHz for sub-register @ref SR_CLKM_CTRL */
//#define CLKM_4MHz (3)
///** Constant CLKM_8MHz for sub-register @ref SR_CLKM_CTRL */
//#define CLKM_8MHz (4)
///** Constant CLKM_16MHz for sub-register @ref SR_CLKM_CTRL */
//#define CLKM_16MHz (5)
///** Offset for register PHY_TX_PWR */
//#define RG_PHY_TX_PWR (0x05)
///** Access parameters for sub-register TX_AUTO_CRC_ON in register @ref RG_PHY_TX_PWR */
//#define SR_TX_AUTO_CRC_ON 0x05, 0x80, 7
//#define SR_reserved_05_2 0x05, 0x70, 4
///** Access parameters for sub-register TX_PWR in register @ref RG_PHY_TX_PWR */
//#define SR_TX_PWR 0x05, 0x0f, 0
///** Offset for register PHY_RSSI */
//#define RG_PHY_RSSI (0x06)
//#define SR_reserved_06_1 0x06, 0xe0, 5
///** Access parameters for sub-register RSSI in register @ref RG_PHY_RSSI */
//#define SR_RSSI 0x06, 0x1f, 0
///** Offset for register PHY_ED_LEVEL */
//#define RG_PHY_ED_LEVEL (0x07)
///** Access parameters for sub-register ED_LEVEL in register @ref RG_PHY_ED_LEVEL */
//#define SR_ED_LEVEL 0x07, 0xff, 0
///** Offset for register PHY_CC_CCA */
//#define RG_PHY_CC_CCA (0x08)
///** Access parameters for sub-register CCA_REQUEST in register @ref RG_PHY_CC_CCA */
//#define SR_CCA_REQUEST 0x08, 0x80, 7
///** Access parameters for sub-register CCA_MODE in register @ref RG_PHY_CC_CCA */
//#define SR_CCA_MODE 0x08, 0x60, 5
///** Access parameters for sub-register CHANNEL in register @ref RG_PHY_CC_CCA */
//#define SR_CHANNEL 0x08, 0x1f, 0
///** Offset for register CCA_THRES */
//#define RG_CCA_THRES (0x09)
///** Access parameters for sub-register CCA_CS_THRES in register @ref RG_CCA_THRES */
//#define SR_CCA_CS_THRES 0x09, 0xf0, 4
///** Access parameters for sub-register CCA_ED_THRES in register @ref RG_CCA_THRES */
//#define SR_CCA_ED_THRES 0x09, 0x0f, 0
///** Offset for register IRQ_MASK */
//#define RG_IRQ_MASK (0x0e)
///** Access parameters for sub-register IRQ_MASK in register @ref RG_IRQ_MASK */
//#define SR_IRQ_MASK 0x0e, 0xff, 0
///** Offset for register IRQ_STATUS */
//#define RG_IRQ_STATUS (0x0f)
///** Access parameters for sub-register IRQ_7_BAT_LOW in register @ref RG_IRQ_STATUS */
//#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
///** Access parameters for sub-register IRQ_6_TRX_UR in register @ref RG_IRQ_STATUS */
//#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
///** Access parameters for sub-register IRQ_5 in register @ref RG_IRQ_STATUS */
//#define SR_IRQ_5 0x0f, 0x20, 5
///** Access parameters for sub-register IRQ_4 in register @ref RG_IRQ_STATUS */
//#define SR_IRQ_4 0x0f, 0x10, 4
///** Access parameters for sub-register IRQ_3_TRX_END in register @ref RG_IRQ_STATUS */
//#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
///** Access parameters for sub-register IRQ_2_RX_START in register @ref RG_IRQ_STATUS */
//#define SR_IRQ_2_RX_START 0x0f, 0x04, 2
///** Access parameters for sub-register IRQ_1_PLL_UNLOCK in register @ref RG_IRQ_STATUS */
//#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
///** Access parameters for sub-register IRQ_0_PLL_LOCK in register @ref RG_IRQ_STATUS */
//#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
///** Offset for register VREG_CTRL */
//#define RG_VREG_CTRL (0x10)
///** Access parameters for sub-register AVREG_EXT in register @ref RG_VREG_CTRL */
//#define SR_AVREG_EXT 0x10, 0x80, 7
///** Access parameters for sub-register AVDD_OK in register @ref RG_VREG_CTRL */
//#define SR_AVDD_OK 0x10, 0x40, 6
///** Access parameters for sub-register AVREG_TRIM in register @ref RG_VREG_CTRL */
//#define SR_AVREG_TRIM 0x10, 0x30, 4
///** Constant AVREG_1_80V for sub-register @ref SR_AVREG_TRIM */
//#define AVREG_1_80V (0)
///** Constant AVREG_1_75V for sub-register @ref SR_AVREG_TRIM */
//#define AVREG_1_75V (1)
///** Constant AVREG_1_84V for sub-register @ref SR_AVREG_TRIM */
//#define AVREG_1_84V (2)
///** Constant AVREG_1_88V for sub-register @ref SR_AVREG_TRIM */
//#define AVREG_1_88V (3)
///** Access parameters for sub-register DVREG_EXT in register @ref RG_VREG_CTRL */
//#define SR_DVREG_EXT 0x10, 0x08, 3
///** Access parameters for sub-register DVDD_OK in register @ref RG_VREG_CTRL */
//#define SR_DVDD_OK 0x10, 0x04, 2
///** Access parameters for sub-register DVREG_TRIM in register @ref RG_VREG_CTRL */
//#define SR_DVREG_TRIM 0x10, 0x03, 0
///** Constant DVREG_1_80V for sub-register @ref SR_DVREG_TRIM */
//#define DVREG_1_80V (0)
///** Constant DVREG_1_75V for sub-register @ref SR_DVREG_TRIM */
//#define DVREG_1_75V (1)
///** Constant DVREG_1_84V for sub-register @ref SR_DVREG_TRIM */
//#define DVREG_1_84V (2)
///** Constant DVREG_1_88V for sub-register @ref SR_DVREG_TRIM */
//#define DVREG_1_88V (3)
///** Offset for register BATMON */
//#define RG_BATMON (0x11)
//#define SR_reserved_11_1 0x11, 0xc0, 6
///** Access parameters for sub-register BATMON_OK in register @ref RG_BATMON */
//#define SR_BATMON_OK 0x11, 0x20, 5
///** Access parameters for sub-register BATMON_HR in register @ref RG_BATMON */
//#define SR_BATMON_HR 0x11, 0x10, 4
///** Access parameters for sub-register BATMON_VTH in register @ref RG_BATMON */
//#define SR_BATMON_VTH 0x11, 0x0f, 0
///** Offset for register XOSC_CTRL */
//#define RG_XOSC_CTRL (0x12)
///** Offset for register RX_SYN */
//#define RG_RX_SYN 0x15
///** Offset for register XAH_CTRL_1 */
//#define RG_XAH_CTRL_1 0x17
///** Access parameters for sub-register XTAL_MODE in register @ref RG_XOSC_CTRL */
//#define SR_XTAL_MODE 0x12, 0xf0, 4
///** Access parameters for sub-register XTAL_TRIM in register @ref RG_XOSC_CTRL */
//#define SR_XTAL_TRIM 0x12, 0x0f, 0
///** Offset for register FTN_CTRL */
//#define RG_FTN_CTRL (0x18)
///** Access parameters for sub-register FTN_START in register @ref RG_FTN_CTRL */
//#define SR_FTN_START 0x18, 0x80, 7
//#define SR_reserved_18_2 0x18, 0x40, 6
///** Access parameters for sub-register FTNV in register @ref RG_FTN_CTRL */
//#define SR_FTNV 0x18, 0x3f, 0
///** Offset for register PLL_CF */
//#define RG_PLL_CF (0x1a)
///** Access parameters for sub-register PLL_CF_START in register @ref RG_PLL_CF */
//#define SR_PLL_CF_START 0x1a, 0x80, 7
//#define SR_reserved_1a_2 0x1a, 0x70, 4
///** Access parameters for sub-register PLL_CF in register @ref RG_PLL_CF */
//#define SR_PLL_CF 0x1a, 0x0f, 0
///** Offset for register PLL_DCU */
//#define RG_PLL_DCU (0x1b)
///** Access parameters for sub-register PLL_DCU_START in register @ref RG_PLL_DCU */
//#define SR_PLL_DCU_START 0x1b, 0x80, 7
//#define SR_reserved_1b_2 0x1b, 0x40, 6
///** Access parameters for sub-register PLL_DCUW in register @ref RG_PLL_DCU */
//#define SR_PLL_DCUW 0x1b, 0x3f, 0
///** Offset for register PART_NUM */
//#define RG_PART_NUM (0x1c)
///** Access parameters for sub-register PART_NUM in register @ref RG_PART_NUM */
//#define SR_PART_NUM 0x1c, 0xff, 0
///** Constant RF230 for sub-register @ref SR_PART_NUM */
//#define RF230 (2)
///** Offset for register VERSION_NUM */
//#define RG_VERSION_NUM (0x1d)
///** Access parameters for sub-register VERSION_NUM in register @ref RG_VERSION_NUM */
//#define SR_VERSION_NUM 0x1d, 0xff, 0
///** Offset for register MAN_ID_0 */
//#define RG_MAN_ID_0 (0x1e)
///** Access parameters for sub-register MAN_ID_0 in register @ref RG_MAN_ID_0 */
//#define SR_MAN_ID_0 0x1e, 0xff, 0
///** Offset for register MAN_ID_1 */
//#define RG_MAN_ID_1 (0x1f)
///** Access parameters for sub-register MAN_ID_1 in register @ref RG_MAN_ID_1 */
//#define SR_MAN_ID_1 0x1f, 0xff, 0
///** Offset for register SHORT_ADDR_0 */
//#define RG_SHORT_ADDR_0 (0x20)
///** Access parameters for sub-register SHORT_ADDR_0 in register @ref RG_SHORT_ADDR_0 */
//#define SR_SHORT_ADDR_0 0x20, 0xff, 0
///** Offset for register SHORT_ADDR_1 */
//#define RG_SHORT_ADDR_1 (0x21)
///** Access parameters for sub-register SHORT_ADDR_1 in register @ref RG_SHORT_ADDR_1 */
//#define SR_SHORT_ADDR_1 0x21, 0xff, 0
///** Offset for register PAN_ID_0 */
//#define RG_PAN_ID_0 (0x22)
///** Access parameters for sub-register PAN_ID_0 in register @ref RG_PAN_ID_0 */
//#define SR_PAN_ID_0 0x22, 0xff, 0
///** Offset for register PAN_ID_1 */
//#define RG_PAN_ID_1 (0x23)
///** Access parameters for sub-register PAN_ID_1 in register @ref RG_PAN_ID_1 */
//#define SR_PAN_ID_1 0x23, 0xff, 0
///** Offset for register IEEE_ADDR_0 */
//#define RG_IEEE_ADDR_0 (0x24)
///** Access parameters for sub-register IEEE_ADDR_0 in register @ref RG_IEEE_ADDR_0 */
//#define SR_IEEE_ADDR_0 0x24, 0xff, 0
///** Offset for register IEEE_ADDR_1 */
//#define RG_IEEE_ADDR_1 (0x25)
///** Access parameters for sub-register IEEE_ADDR_1 in register @ref RG_IEEE_ADDR_1 */
//#define SR_IEEE_ADDR_1 0x25, 0xff, 0
///** Offset for register IEEE_ADDR_2 */
//#define RG_IEEE_ADDR_2 (0x26)
///** Access parameters for sub-register IEEE_ADDR_2 in register @ref RG_IEEE_ADDR_2 */
//#define SR_IEEE_ADDR_2 0x26, 0xff, 0
///** Offset for register IEEE_ADDR_3 */
//#define RG_IEEE_ADDR_3 (0x27)
///** Access parameters for sub-register IEEE_ADDR_3 in register @ref RG_IEEE_ADDR_3 */
//#define SR_IEEE_ADDR_3 0x27, 0xff, 0
///** Offset for register IEEE_ADDR_4 */
//#define RG_IEEE_ADDR_4 (0x28)
///** Access parameters for sub-register IEEE_ADDR_4 in register @ref RG_IEEE_ADDR_4 */
//#define SR_IEEE_ADDR_4 0x28, 0xff, 0
///** Offset for register IEEE_ADDR_5 */
//#define RG_IEEE_ADDR_5 (0x29)
///** Access parameters for sub-register IEEE_ADDR_5 in register @ref RG_IEEE_ADDR_5 */
//#define SR_IEEE_ADDR_5 0x29, 0xff, 0
///** Offset for register IEEE_ADDR_6 */
//#define RG_IEEE_ADDR_6 (0x2a)
///** Access parameters for sub-register IEEE_ADDR_6 in register @ref RG_IEEE_ADDR_6 */
//#define SR_IEEE_ADDR_6 0x2a, 0xff, 0
///** Offset for register IEEE_ADDR_7 */
//#define RG_IEEE_ADDR_7 (0x2b)
///** Access parameters for sub-register IEEE_ADDR_7 in register @ref RG_IEEE_ADDR_7 */
//#define SR_IEEE_ADDR_7 0x2b, 0xff, 0
///** Offset for register XAH_CTRL */
//#define RG_XAH_CTRL_0 (0x2c)
///** Access parameters for sub-register MAX_FRAME_RETRIES in register @ref RG_XAH_CTRL_0 */
//#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
///** Access parameters for sub-register MAX_CSMA_RETRIES in register @ref RG_XAH_CTRL_0 */
//#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
//#define SR_reserved_2c_3 0x2c, 0x01, 0
///** Offset for register CSMA_SEED_0 */
//#define RG_CSMA_SEED_0 (0x2d)
///** Access parameters for sub-register CSMA_SEED_0 in register @ref RG_CSMA_SEED_0 */
//#define SR_CSMA_SEED_0 0x2d, 0xff, 0
///** Offset for register CSMA_SEED_1 */
//#define RG_CSMA_SEED_1 (0x2e)
///** Offset for register CSMA_BE */
//#define RG_CSMA_BE 0x2f
///** Access parameters for sub-register MIN_BE in register @ref RG_CSMA_SEED_1 */
//#define SR_MIN_BE 0x2e, 0xc0, 6
//#define SR_reserved_2e_2 0x2e, 0x30, 4
///** Access parameters for sub-register I_AM_COORD in register @ref RG_CSMA_SEED_1 */
//#define SR_I_AM_COORD 0x2e, 0x08, 3
///** Access parameters for sub-register CSMA_SEED_1 in register @ref RG_CSMA_SEED_1 */
//#define SR_CSMA_SEED_1 0x2e, 0x07, 0
#endif
#endif /* PHY256RFR2y_REGISTERMAP_EXTERNAL_H */

12
cpu/avr/radio/rf230bb/hal.h
View file

@ -78,6 +78,7 @@
#define ZIGBIT 4 #define ZIGBIT 4
#define IRIS 5 #define IRIS 5
#define ATMEGA128RFA1 6 #define ATMEGA128RFA1 6
#define ATMEGA256RFR2 7
#if PLATFORM_TYPE == RCB_B #if PLATFORM_TYPE == RCB_B
/* 1281 rcb */ /* 1281 rcb */
@ -145,6 +146,11 @@
# define SLPTRPORT TRXPR # define SLPTRPORT TRXPR
# define SLPTRPIN 1 # define SLPTRPIN 1
#elif PLATFORM_TYPE == ATMEGA256RFR2
/* ATmega1281 with internal AT86RF231 radio */
# define SLPTRPORT TRXPR
# define SLPTRPIN 1
#elif CONTIKI_TARGET_MULLE #elif CONTIKI_TARGET_MULLE
/* mulle 5.2 (TODO: move to platform specific) */ /* mulle 5.2 (TODO: move to platform specific) */
# define SSPORT 3 # define SSPORT 3
@ -233,7 +239,7 @@
* that the source code can directly use. * that the source code can directly use.
* \{ * \{
*/ */
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
#define hal_set_rst_low( ) ( TRXPR &= ~( 1 << TRXRST ) ) /**< This macro pulls the RST pin low. */ #define hal_set_rst_low( ) ( TRXPR &= ~( 1 << TRXRST ) ) /**< This macro pulls the RST pin low. */
#define hal_set_rst_high( ) ( TRXPR |= ( 1 << TRXRST ) ) /**< This macro pulls the RST pin high. */ #define hal_set_rst_high( ) ( TRXPR |= ( 1 << TRXRST ) ) /**< This macro pulls the RST pin high. */
@ -274,7 +280,7 @@
#define HAL_DD_SCK SCKPIN /**< Data Direction bit for SCK. */ #define HAL_DD_SCK SCKPIN /**< Data Direction bit for SCK. */
#define HAL_DD_MOSI MOSIPIN /**< Data Direction bit for MOSI. */ #define HAL_DD_MOSI MOSIPIN /**< Data Direction bit for MOSI. */
#define HAL_DD_MISO MISOPIN /**< Data Direction bit for MISO. */ #define HAL_DD_MISO MISOPIN /**< Data Direction bit for MISO. */
#endif /* defined(__AVR_ATmega128RFA1__) */ #endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega256RFR2__) */
/** \} */ /** \} */
@ -367,7 +373,7 @@ typedef struct{
void hal_init( void ); void hal_init( void );
/* Hack for atmega128rfa1 with integrated radio. Access registers directly, not through SPI */ /* Hack for atmega128rfa1 with integrated radio. Access registers directly, not through SPI */
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
//#define hal_register_read(address) _SFR_MEM8((uint16_t)address) //#define hal_register_read(address) _SFR_MEM8((uint16_t)address)
#define hal_register_read(address) address #define hal_register_read(address) address
uint8_t hal_subregister_read( uint16_t address, uint8_t mask, uint8_t position ); uint8_t hal_subregister_read( uint16_t address, uint8_t mask, uint8_t position );

33
cpu/avr/radio/rf230bb/halbb.c
View file

@ -74,8 +74,9 @@ extern uint8_t debugflowsize,debugflow[DEBUGFLOWSIZE];
#include "hal.h" #include "hal.h"
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__)
#include <avr/io.h>
#include "atmega128rfa1_registermap.h" #include "atmega128rfa1_registermap.h"
#elif defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
#include "atmega256rfr2_registermap.h"
#else #else
#include "at86rf230_registermap.h" #include "at86rf230_registermap.h"
#endif #endif
@ -88,7 +89,7 @@ volatile extern signed char rf230_last_rssi;
/*============================ IMPLEMENTATION ================================*/ /*============================ IMPLEMENTATION ================================*/
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
/* AVR1281 with internal RF231 radio */ /* AVR1281 with internal RF231 radio */
#include <avr/interrupt.h> #include <avr/interrupt.h>
@ -158,8 +159,7 @@ inline uint8_t spiWrite(uint8_t byte)
/** \brief This function initializes the Hardware Abstraction Layer. /** \brief This function initializes the Hardware Abstraction Layer.
*/ */
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
void void
hal_init(void) hal_init(void)
{ {
@ -241,8 +241,7 @@ hal_init(void)
} }
#endif /* !__AVR__ */ #endif /* !__AVR__ */
#if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
#if defined(__AVR_ATmega128RFA1__)
/* Hack for internal radio registers. hal_register_read and hal_register_write are /* Hack for internal radio registers. hal_register_read and hal_register_write are
handled through defines, but the preprocesser can't parse a macro containing handled through defines, but the preprocesser can't parse a macro containing
another #define with multiple arguments, e.g. using another #define with multiple arguments, e.g. using
@ -279,7 +278,7 @@ hal_subregister_write(uint16_t address, uint8_t mask, uint8_t position,
HAL_LEAVE_CRITICAL_REGION(); HAL_LEAVE_CRITICAL_REGION();
} }
#else /* defined(__AVR_ATmega128RFA1__) */ #else /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/** \brief This function reads data from one of the radio transceiver's registers. /** \brief This function reads data from one of the radio transceiver's registers.
* *
@ -383,7 +382,7 @@ hal_subregister_write(uint8_t address, uint8_t mask, uint8_t position,
/* Write the modified register value. */ /* Write the modified register value. */
hal_register_write(address, value); hal_register_write(address, value);
} }
#endif /* defined(__AVR_ATmega128RFA1__) */ #endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/** \brief Transfer a frame from the radio transceiver to a RAM buffer /** \brief Transfer a frame from the radio transceiver to a RAM buffer
* *
@ -399,7 +398,7 @@ hal_subregister_write(uint8_t address, uint8_t mask, uint8_t position,
void void
hal_frame_read(hal_rx_frame_t *rx_frame) hal_frame_read(hal_rx_frame_t *rx_frame)
{ {
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
uint8_t frame_length,*rx_data,*rx_buffer; uint8_t frame_length,*rx_data,*rx_buffer;
@ -432,7 +431,7 @@ hal_frame_read(hal_rx_frame_t *rx_frame)
*/ */
rx_frame->crc = true; rx_frame->crc = true;
#else /* defined(__AVR_ATmega128RFA1__) */ #else /* */
uint8_t frame_length, *rx_data; uint8_t frame_length, *rx_data;
@ -487,7 +486,7 @@ hal_frame_read(hal_rx_frame_t *rx_frame)
HAL_SPI_TRANSFER_CLOSE(); HAL_SPI_TRANSFER_CLOSE();
#endif /* defined(__AVR_ATmega128RFA1__) */ #endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
} }
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -500,7 +499,7 @@ hal_frame_read(hal_rx_frame_t *rx_frame)
void void
hal_frame_write(uint8_t *write_buffer, uint8_t length) hal_frame_write(uint8_t *write_buffer, uint8_t length)
{ {
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
uint8_t *tx_buffer; uint8_t *tx_buffer;
tx_buffer=(uint8_t *)0x180; //start of fifo in i/o space tx_buffer=(uint8_t *)0x180; //start of fifo in i/o space
/* Write frame length, including the two byte checksum */ /* Write frame length, including the two byte checksum */
@ -518,7 +517,7 @@ hal_frame_write(uint8_t *write_buffer, uint8_t length)
#endif #endif
do _SFR_MEM8(tx_buffer++)= *write_buffer++; while (--length); do _SFR_MEM8(tx_buffer++)= *write_buffer++; while (--length);
#else /* defined(__AVR_ATmega128RFA1__) */ #else /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
/* Optionally truncate length to maximum frame length. /* Optionally truncate length to maximum frame length.
* Not doing this is a fast way to know when the application needs fixing! * Not doing this is a fast way to know when the application needs fixing!
*/ */
@ -540,7 +539,7 @@ hal_frame_write(uint8_t *write_buffer, uint8_t length)
do HAL_SPI_TRANSFER(*write_buffer++); while (--length); do HAL_SPI_TRANSFER(*write_buffer++); while (--length);
HAL_SPI_TRANSFER_CLOSE(); HAL_SPI_TRANSFER_CLOSE();
#endif /* defined(__AVR_ATmega128RFA1__) */ #endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
} }
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -632,7 +631,7 @@ volatile char rf230interruptflag;
#define INTERRUPTDEBUG(arg) #define INTERRUPTDEBUG(arg)
#endif #endif
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
/* The atmega128rfa1 has individual interrupts for the integrated radio' /* The atmega128rfa1 has individual interrupts for the integrated radio'
* Whichever are enabled by the RF230 driver must be present even if not used! * Whichever are enabled by the RF230 driver must be present even if not used!
*/ */
@ -713,7 +712,7 @@ ISR(TRX24_CCA_ED_DONE_vect)
rf230_ccawait=0; rf230_ccawait=0;
} }
#else /* defined(__AVR_ATmega128RFA1__) */ #else /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
/* Separate RF230 has a single radio interrupt and the source must be read from the IRQ_STATUS register */ /* Separate RF230 has a single radio interrupt and the source must be read from the IRQ_STATUS register */
HAL_RF230_ISR() HAL_RF230_ISR()
{ {
@ -803,7 +802,7 @@ HAL_RF230_ISR()
; ;
} }
} }
#endif /* defined(__AVR_ATmega128RFA1__) */ #endif /* defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__) */
# endif /* defined(DOXYGEN) */ # endif /* defined(DOXYGEN) */
/** @} */ /** @} */

49
cpu/avr/radio/rf230bb/rf230bb.c
View file

@ -212,7 +212,7 @@ static unsigned long total_time_for_transmission, total_transmission_len;
static int num_transmissions; static int num_transmissions;
#endif #endif
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
volatile uint8_t rf230_wakewait, rf230_txendwait, rf230_ccawait; volatile uint8_t rf230_wakewait, rf230_txendwait, rf230_ccawait;
#endif #endif
@ -433,7 +433,21 @@ rf230_waitidle(void)
} }
} }
/*----------------------------------------------------------------------------*/ /* Set reduced power consumption for AtMegaXXXRFR2 MCU's. See AT02594 */
static uint8_t rpc = 0xFF; /* Default max power save */
void
rf230_set_rpc(uint8_t data)
{
rpc = data;
}
uint8_t
rf230_get_rpc(void)
{
return rpc;
}
/** \brief This function will change the current state of the radio /** \brief This function will change the current state of the radio
* transceiver's internal state machine. * transceiver's internal state machine.
* *
@ -507,6 +521,10 @@ radio_set_trx_state(uint8_t new_state)
/* When the PLL is active most states can be reached in 1us. However, from */ /* When the PLL is active most states can be reached in 1us. However, from */
/* TRX_OFF the PLL needs time to activate. */ /* TRX_OFF the PLL needs time to activate. */
if (current_state == TRX_OFF){ if (current_state == TRX_OFF){
#if defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
hal_subregister_write(SR_TRX_RPC, rpc); /* Enable RPC features */
#endif
delay_us(TIME_TRX_OFF_TO_PLL_ACTIVE); delay_us(TIME_TRX_OFF_TO_PLL_ACTIVE);
} else { } else {
delay_us(TIME_STATE_TRANSITION_PLL_ACTIVE); delay_us(TIME_STATE_TRANSITION_PLL_ACTIVE);
@ -535,7 +553,7 @@ rf230_set_promiscuous_mode(bool isPromiscuous) {
#if RF230_CONF_AUTOACK #if RF230_CONF_AUTOACK
is_promiscuous = isPromiscuous; is_promiscuous = isPromiscuous;
/* TODO: Figure out when to pass promisc state to 802.15.4 */ /* TODO: Figure out when to pass promisc state to 802.15.4 */
// radio_set_trx_state(is_promiscuous?RX_ON:RX_AACK_ON); radio_set_trx_state(is_promiscuous?RX_ON:RX_AACK_ON);
#endif #endif
} }
@ -585,7 +603,7 @@ radio_on(void)
#if RF230BB_CONF_LEDONPORTE1 #if RF230BB_CONF_LEDONPORTE1
PORTE|=(1<<PE1); //ledon PORTE|=(1<<PE1); //ledon
#endif #endif
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
/* Use the poweron interrupt for delay */ /* Use the poweron interrupt for delay */
rf230_wakewait=1; rf230_wakewait=1;
{ {
@ -937,7 +955,7 @@ rf230_transmit(unsigned short payload_len)
/* If radio is sleeping we have to turn it on first */ /* If radio is sleeping we have to turn it on first */
/* This automatically does the PLL calibrations */ /* This automatically does the PLL calibrations */
if (hal_get_slptr()) { if (hal_get_slptr()) {
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
ENERGEST_ON(ENERGEST_TYPE_LED_RED); ENERGEST_ON(ENERGEST_TYPE_LED_RED);
#if RF230BB_CONF_LEDONPORTE1 #if RF230BB_CONF_LEDONPORTE1
PORTE|=(1<<PE1); //ledon PORTE|=(1<<PE1); //ledon
@ -1383,6 +1401,25 @@ PROCESS_THREAD(rf230_process, ev, data)
/* Restore interrupts. */ /* Restore interrupts. */
HAL_LEAVE_CRITICAL_REGION(); HAL_LEAVE_CRITICAL_REGION();
PRINTF("rf230_read: %u bytes lqi %u\n",len,rf230_last_correlation); PRINTF("rf230_read: %u bytes lqi %u\n",len,rf230_last_correlation);
if(is_promiscuous) {
uint8_t i;
unsigned const char * rxdata = packetbuf_dataptr();
/* Print magic */
putchar(0xC1);
putchar(0x1F);
putchar(0xFE);
putchar(0x72);
/* Print version */
putchar(0x01);
/* Print CMD == frame */
putchar(0x00);
putchar(len+3);
for (i=0;i<len;i++) putchar(rxdata[i]);
printf("\n");
}
#if DEBUG>1 #if DEBUG>1
{ {
uint8_t i; uint8_t i;
@ -1658,7 +1695,7 @@ rf230_cca(void)
/* Start the CCA, wait till done, return result */ /* Start the CCA, wait till done, return result */
/* Note reading the TRX_STATUS register clears both CCA_STATUS and CCA_DONE bits */ /* Note reading the TRX_STATUS register clears both CCA_STATUS and CCA_DONE bits */
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
#if 1 //interrupt method #if 1 //interrupt method
/* Disable rx transitions to busy (RX_PDT_BIT) */ /* Disable rx transitions to busy (RX_PDT_BIT) */
/* Note: for speed this resets rx threshold to the compiled default */ /* Note: for speed this resets rx threshold to the compiled default */

6
cpu/avr/radio/rf230bb/rf230bb.h
View file

@ -57,6 +57,8 @@
#include "hal.h" #include "hal.h"
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__)
#include "atmega128rfa1_registermap.h" #include "atmega128rfa1_registermap.h"
#elif defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
#include "atmega256rfr2_registermap.h"
#else #else
#include "at86rf230_registermap.h" #include "at86rf230_registermap.h"
#endif #endif
@ -68,7 +70,7 @@
#define RF230_REVB ( 2 ) #define RF230_REVB ( 2 )
#define SUPPORTED_MANUFACTURER_ID ( 31 ) #define SUPPORTED_MANUFACTURER_ID ( 31 )
#if defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
#define RF230_SUPPORTED_INTERRUPT_MASK ( 0xFF ) #define RF230_SUPPORTED_INTERRUPT_MASK ( 0xFF )
#else #else
/* RF230 does not support RX_START interrupts in extended mode, but it seems harmless to always enable it. */ /* RF230 does not support RX_START interrupts in extended mode, but it seems harmless to always enable it. */
@ -215,6 +217,8 @@ uint8_t rf230_get_channel(void);
void rf230_set_pan_addr(unsigned pan,unsigned addr,const uint8_t ieee_addr[8]); void rf230_set_pan_addr(unsigned pan,unsigned addr,const uint8_t ieee_addr[8]);
void rf230_set_txpower(uint8_t power); void rf230_set_txpower(uint8_t power);
uint8_t rf230_get_txpower(void); uint8_t rf230_get_txpower(void);
void rf230_set_rpc(uint8_t rpc);
uint8_t rf230_get_rpc(void);
void rf230_set_promiscuous_mode(bool isPromiscuous); void rf230_set_promiscuous_mode(bool isPromiscuous);
bool rf230_is_ready_to_send(); bool rf230_is_ready_to_send();

2
cpu/avr/rtimer-arch.c
View file

@ -64,7 +64,7 @@
#define OCF3C OCF3B #define OCF3C OCF3B
#endif #endif
#if defined(__AVR_ATmega1281__) || defined(__AVR_AT90USB1287__) || defined(__AVR_ATmega128RFA1__) #if defined(__AVR_ATmega1281__) || defined(__AVR_AT90USB1287__) || defined(__AVR_ATmega128RFA1__) || defined(__AVR_ATmega128RFR2__) || defined(__AVR_ATmega256RFR2__)
#define ETIMSK TIMSK3 #define ETIMSK TIMSK3
#define ETIFR TIFR3 #define ETIFR TIFR3
#define TICIE3 ICIE3 #define TICIE3 ICIE3