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Merge branch 'contiki' into osd

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This commit is contained in:
Harald Pichler 2015-02-18 10:04:47 +01:00
commit d31ecbf486
116 changed files with 5024 additions and 1427 deletions
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4
cpu/arm/aducrf101/Makefile.aducrf101.gnu
View file

@ -39,8 +39,8 @@ CROSS_COMPILE = arm-none-eabi-
CC = $(CROSS_COMPILE)gcc
LD = $(CROSS_COMPILE)gcc
AS = $(CROSS_COMPILE)gcc
AR = $(CROSS_COMPILE)ar
NM = $(CROSS_COMPILE)nm
AR = $(CROSS_COMPILE)gcc-ar
NM = $(CROSS_COMPILE)gcc-nm
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
STRIP = $(CROSS_COMPILE)strip

56
cpu/avr/dev/clock.c
View file

@ -159,7 +159,7 @@ clock_set_seconds(unsigned long sec)
seconds = sec;
}
/*---------------------------------------------------------------------------*/
/**
/*
* Wait for a number of clock ticks.
*/
void
@ -175,7 +175,7 @@ clock_wait(clock_time_t t)
}
}
/*---------------------------------------------------------------------------*/
/**
/*
* Delay the CPU for up to 65535*(4000000/F_CPU) microseconds.
* Copied from _delay_loop_2 in AVR library delay_basic.h, 4 clocks per loop.
* For accurate short delays, inline _delay_loop_2 in the caller, use a constant
@ -193,44 +193,44 @@ my_delay_loop_2(uint16_t __count)
);
}
void
clock_delay_usec(uint16_t howlong)
clock_delay_usec(uint16_t dt)
{
#if 0
/* Accurate delay at any frequency, but introduces a 64 bit intermediate
* and has a 279 clock overhead.
*/
if(howlong<=(uint16_t)(279000000UL/F_CPU)) return;
howlong-=(uint16_t) (279000000UL/F_CPU);
my_delay_loop_2(((uint64_t)(howlong) * (uint64_t) F_CPU) / 4000000ULL);
if(dt<=(uint16_t)(279000000UL/F_CPU)) return;
dt-=(uint16_t) (279000000UL/F_CPU);
my_delay_loop_2(((uint64_t)(dt) * (uint64_t) F_CPU) / 4000000ULL);
/* Remaining numbers tweaked for the breakpoint CPU frequencies */
/* Add other frequencies as necessary */
#elif F_CPU>=16000000UL
if(howlong<1) return;
my_delay_loop_2((howlong*(uint16_t)(F_CPU/3250000)));
if(dt<1) return;
my_delay_loop_2((dt*(uint16_t)(F_CPU/3250000)));
#elif F_CPU >= 12000000UL
if(howlong<2) return;
howlong-=(uint16_t) (3*12000000/F_CPU);
my_delay_loop_2((howlong*(uint16_t)(F_CPU/3250000)));
if(dt<2) return;
dt-=(uint16_t) (3*12000000/F_CPU);
my_delay_loop_2((dt*(uint16_t)(F_CPU/3250000)));
#elif F_CPU >= 8000000UL
if(howlong<4) return;
howlong-=(uint16_t) (3*8000000/F_CPU);
my_delay_loop_2((howlong*(uint16_t)(F_CPU/2000000))/2);
if(dt<4) return;
dt-=(uint16_t) (3*8000000/F_CPU);
my_delay_loop_2((dt*(uint16_t)(F_CPU/2000000))/2);
#elif F_CPU >= 4000000UL
if(howlong<5) return;
howlong-=(uint16_t) (4*4000000/F_CPU);
my_delay_loop_2((howlong*(uint16_t)(F_CPU/2000000))/2);
if(dt<5) return;
dt-=(uint16_t) (4*4000000/F_CPU);
my_delay_loop_2((dt*(uint16_t)(F_CPU/2000000))/2);
#elif F_CPU >= 2000000UL
if(howlong<11) return;
howlong-=(uint16_t) (10*2000000/F_CPU);
my_delay_loop_2((howlong*(uint16_t)(F_CPU/1000000))/4);
if(dt<11) return;
dt-=(uint16_t) (10*2000000/F_CPU);
my_delay_loop_2((dt*(uint16_t)(F_CPU/1000000))/4);
#elif F_CPU >= 1000000UL
if(howlong<=17) return;
howlong-=(uint16_t) (17*1000000/F_CPU);
my_delay_loop_2((howlong*(uint16_t)(F_CPU/1000000))/4);
if(dt<=17) return;
dt-=(uint16_t) (17*1000000/F_CPU);
my_delay_loop_2((dt*(uint16_t)(F_CPU/1000000))/4);
#else
howlong >> 5;
if (howlong < 1) return;
my_delay_loop_2(howlong);
dt >> 5;
if (dt < 1) return;
my_delay_loop_2(dt);
#endif
}
#if 0
@ -250,7 +250,7 @@ clock_delay(unsigned int howlong)
/*---------------------------------------------------------------------------*/
/**
* Delay up to 65535 milliseconds.
* \param dt How many milliseconds to delay.
* \param howlong How many milliseconds to delay.
*
* Neither interrupts nor the watchdog timer is disabled over the delay.
* Platforms are not required to implement this call.
@ -279,7 +279,7 @@ clock_delay_msec(uint16_t howlong)
/*---------------------------------------------------------------------------*/
/**
* Adjust the system current clock time.
* \param dt How many ticks to add
* \param howmany How many ticks to add
*
* Typically used to add ticks after an MCU sleep
* clock_seconds will increment if necessary to reflect the tick addition.

4
cpu/cc2430/dev/clock.c
View file

@ -54,7 +54,7 @@ static unsigned long timer_value;
static volatile CC_AT_DATA clock_time_t count = 0; /* Uptime in ticks */
static volatile CC_AT_DATA clock_time_t seconds = 0; /* Uptime in secs */
/*---------------------------------------------------------------------------*/
/**
/*
* Each iteration is ~1.0xy usec, so this function delays for roughly len usec
*/
void
@ -68,7 +68,7 @@ clock_delay_usec(uint16_t len)
ENABLE_INTERRUPTS();
}
/*---------------------------------------------------------------------------*/
/**
/*
* Wait for a multiple of ~8 ms (a tick)
*/
void

9
cpu/cc2538/clock.c
View file

@ -136,16 +136,15 @@ clock_wait(clock_time_t i)
while(clock_time() - start < (clock_time_t)i);
}
/*---------------------------------------------------------------------------*/
/**
* \brief Arch-specific implementation of clock_delay_usec for the cc2538
* \param len Delay \e len uSecs
/*
* Arch-specific implementation of clock_delay_usec for the cc2538
*
* See clock_init() for GPT0 Timer A's configuration
*/
void
clock_delay_usec(uint16_t len)
clock_delay_usec(uint16_t dt)
{
REG(GPT_0_BASE | GPTIMER_TAILR) = len;
REG(GPT_0_BASE | GPTIMER_TAILR) = dt;
REG(GPT_0_BASE | GPTIMER_CTL) |= GPTIMER_CTL_TAEN;
/* One-Shot mode: TAEN will be cleared when the timer reaches 0 */

15
cpu/cc2538/cpu.h
View file

@ -29,12 +29,21 @@
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \addtogroup cc2538
* \addtogroup platform
* @{
*
* \defgroup cc2538-platforms TI cc2538-powered platforms
*
* Documentation for all platforms powered by the TI cc2538 System-on-Chip
* @{
*
* \defgroup cc2538 The TI cc2538 System-on-Chip
* CPU-Specific functionality - available to all cc2538-based platforms
* @{
*
* \defgroup cc2538-cpu cc2538 CPU
*
* cc2538 CPU-specific functions for the cc2538 core
* CPU-specific functions for the cc2538 core
* @{
*
* \file
@ -60,6 +69,8 @@ unsigned long cpu_cpsie(void);
#endif /* CPU_H_ */
/**
* @}
* @}
* @}
* @}
*/

2
cpu/cc2538/dbg.h
View file

@ -34,7 +34,7 @@
*
* \defgroup cc2538-char-io cc2538 Character I/O
*
* cc2538 CPU-specific functions for debugging and SLIP I/O
* CPU-specific functions for debugging and SLIP I/O
*
* On the cc2538, character I/O can be directed over USB or UART. This is
* controlled by a series of configuration directives:

30
cpu/cc2538/dev/cc2538-rf.c
View file

@ -122,6 +122,7 @@ static const uint8_t magic[] = { 0x53, 0x6E, 0x69, 0x66 }; /** Snif */
#endif
/*---------------------------------------------------------------------------*/
static uint8_t rf_flags;
static uint8_t rf_channel = CC2538_RF_CHANNEL;
static int on(void);
static int off(void);
@ -186,10 +187,22 @@ set_channel(uint8_t channel)
}
/* Changes to FREQCTRL take effect after the next recalibration */
off();
/* If we are off, save state, otherwise switch off and save state */
if((REG(RFCORE_XREG_FSMSTAT0) & RFCORE_XREG_FSMSTAT0_FSM_FFCTRL_STATE) == 0) {
rf_flags |= WAS_OFF;
} else {
rf_flags &= ~WAS_OFF;
off();
}
REG(RFCORE_XREG_FREQCTRL) = (CC2538_RF_CHANNEL_MIN
+ (channel - CC2538_RF_CHANNEL_MIN) * CC2538_RF_CHANNEL_SPACING);
on();
/* switch radio back on only if radio was on before - otherwise will turn on radio foor sleepy nodes */
if((rf_flags & WAS_OFF) != WAS_OFF) {
on();
}
rf_channel = channel;
return (int8_t) channel;
}
@ -445,7 +458,7 @@ init(void)
/* Set TX Power */
REG(RFCORE_XREG_TXPOWER) = CC2538_RF_TX_POWER;
set_channel(CC2538_RF_CHANNEL);
set_channel(rf_channel);
/* Acknowledge RF interrupts, FIFOP only */
REG(RFCORE_XREG_RFIRQM0) |= RFCORE_XREG_RFIRQM0_FIFOP;
@ -951,10 +964,21 @@ PROCESS_THREAD(cc2538_rf_process, ev, data)
/* If we were polled due to an RF error, reset the transceiver */
if(rf_flags & RF_MUST_RESET) {
uint8_t was_on;
rf_flags = 0;
/* save state so we know if to switch on again after re-init */
if((REG(RFCORE_XREG_FSMSTAT0) & RFCORE_XREG_FSMSTAT0_FSM_FFCTRL_STATE) == 0) {
was_on = 0;
} else {
was_on = 1;
}
off();
init();
if(was_on) {
/* switch back on */
on();
}
}
}

24
cpu/cc2538/dev/gpio.h
View file

@ -117,6 +117,20 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
/** \brief Set pins with PIN_MASK of port with PORT_BASE to value.
* \param PORT_BASE GPIO Port register offset
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
* \param value The new value to write to the register. Only pins specified
* by PIN_MASK will be set.
*
* \note The outcome of this macro invocation will be to write to the register
* a new value for multiple pins. For that reason, the value argument cannot be
* a simple 0 or 1. Instead, it must be the value corresponding to the pins that
* you wish to set.
*
* Thus, if you only want to set a single pin (e.g. pin 2), do \e not pass 1,
* but you must pass 0x04 instead (1 << 2). This may seem counter-intuitive at
* first glance, but it allows a single invocation of this macro to set
* multiple pins in one go if so desired. For example, you can set pins 3 and 1
* and the same time clear pins 2 and 0. To do so, pass 0x0F as the PIN_MASK
* and then use 0x0A as the value ((1 << 3) | (1 << 1) for pins 3 and 1)
*/
#define GPIO_WRITE_PIN(PORT_BASE, PIN_MASK, value) \
do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = (value); } while(0)
@ -124,6 +138,12 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
/** \brief Read pins with PIN_MASK of port with PORT_BASE.
* \param PORT_BASE GPIO Port register offset
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
* \return The value of the pins specified by PIN_MASK
*
* This macro will \e not return 0 or 1. Instead, it will return the values of
* the pins specified by PIN_MASK ORd together. Thus, if you pass 0xC3
* (0x80 | 0x40 | 0x02 | 0x01) as the PIN_MASK and pins 7 and 0 are high,
* the macro will return 0x81.
*/
#define GPIO_READ_PIN(PORT_BASE, PIN_MASK) \
REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2))
@ -261,7 +281,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
/**
* \brief Converts a pin number to a pin mask
* \param The pin number in the range [0..7]
* \param PIN The pin number in the range [0..7]
* \return A pin mask which can be used as the PIN_MASK argument of the macros
* in this category
*/
@ -269,7 +289,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
/**
* \brief Converts a port number to the port base address
* \param The port number in the range 0 - 3. Likely GPIO_X_NUM.
* \param PORT The port number in the range 0 - 3. Likely GPIO_X_NUM.
* \return The base address for the registers corresponding to that port
* number.
*/

2
cpu/cc2538/dev/ioc.h
View file

@ -34,7 +34,7 @@
*
* \defgroup cc2538-ioc cc2538 I/O Control
*
* cc2538 I/O Control Module
* Driver for the cc2538 I/O Control Module
* @{
*
* \file

4
cpu/cc2538/dev/scb.h
View file

@ -32,7 +32,9 @@
* \addtogroup cc2538
* @{
*
* \defgroup cc2538-scb cc2538 System Control Block
* \defgroup cc2538-scb cc2538 System Control Block (SCB)
*
* Offsets and bit definitions for SCB registers
* @{
*
* \file

8
cpu/cc2538/dev/spi.c
View file

@ -31,7 +31,7 @@
* @{
*
* \file
* Implementation of the cc2538 SPI peripheral
* Implementation of the cc2538 SPI peripheral driver
*/
#include "contiki.h"
#include "reg.h"
@ -52,7 +52,7 @@
/**
* \brief Initialize the SPI bus.
*
* This SPI init() function uses the following #defines to set the pins:
* This SPI init() function uses the following defines to set the pins:
* SPI_CLK_PORT SPI_CLK_PIN
* SPI_MOSI_PORT SPI_MOSI_PIN
* SPI_MISO_PORT SPI_MISO_PIN
@ -126,7 +126,9 @@ spi_disable(void)
REG(SYS_CTRL_RCGCSSI) &= ~1;
}
/*---------------------------------------------------------------------------*/
void spi_set_mode(uint32_t frame_format, uint32_t clock_polarity, uint32_t clock_phase, uint32_t data_size)
void
spi_set_mode(uint32_t frame_format, uint32_t clock_polarity,
uint32_t clock_phase, uint32_t data_size)
{
/* Disable the SSI peripheral to configure it */
REG(SSI0_BASE + SSI_CR1) = 0;

2
cpu/cc2538/dev/sys-ctrl.h
View file

@ -32,7 +32,7 @@
* \addtogroup cc2538
* @{
*
* \defgroup cc2538-sys-ctrl cc2538 System Control
* \defgroup cc2538-sys-ctrl cc2538 System Control (SysCtrl)
*
* Driver for the cc2538 System Control Module
* @{

5
cpu/cc2538/dev/udma.h
View file

@ -560,12 +560,13 @@ void udma_init(void);
/**
* \brief Sets the channels source address
* \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
* \param
* \param src_end The source's end address
*/
void udma_set_channel_src(uint8_t channel, uint32_t src_end);
/**
* \brief
* \brief Sets the channel's destination address
* \param dst_end The destination's end address
* \param channel The channel as a value in [0 , UDMA_CONF_MAX_CHANNEL]
*/
void udma_set_channel_dst(uint8_t channel, uint32_t dst_end);

12
cpu/cc2538/spi-arch.h
View file

@ -27,16 +27,13 @@
* SUCH DAMAGE.
*/
/**
* \addtogroup cc2538
* \addtogroup cc2538-spi
* @{
*
* Implementation of the low-level SPI primitives such as waiting for the TX
* FIFO to be ready, inserting into the TX FIFO, etc.
* @{
*/
/**
* \file
* Header file for the cc2538 SPI commands
* Header file for the cc2538 SPI driver, including macros for the
* implementation of the low-level SPI primitives such as waiting for the TX
* FIFO to be ready, inserting into the TX FIFO, etc.
*/
#ifndef SPI_ARCH_H_
#define SPI_ARCH_H_
@ -121,6 +118,5 @@ void spi_set_mode(uint32_t frame_format, uint32_t clock_polarity,
#endif /* SPI_ARCH_H_ */
/**
* @}
* @}
*/

2
cpu/cc253x/dev/clock.c
View file

@ -70,7 +70,7 @@ clock_delay_usec(uint16_t len)
ENABLE_INTERRUPTS();
}
/*---------------------------------------------------------------------------*/
/**
/*
* Wait for a multiple of ~8 ms (a tick)
*/
void

2
cpu/cc253x/dev/uart0.c
View file

@ -39,7 +39,7 @@ uart0_init()
#else
PERCFG &= ~PERCFG_U0CFG; /* alternative port 1 = P0.5-2 */
#ifdef UART0_RTSCTS
P0SEL |= 0x20 | 0x10; /* peripheral select for TX and RX */
P0SEL |= 0x3C; /* peripheral select for RTS and CTS, TX, RX */
#else
P0SEL |= 0x0C; /* peripheral select for TX and RX */
P0 &= ~0x20; /* RTS down */

8
cpu/mc1322x/clock.c
View file

@ -97,7 +97,7 @@ clock_wait(clock_time_t t)
while ((signed long)(current_clock - endticks) < 0) {;}
}
/*---------------------------------------------------------------------------*/
/**
/*
* Delay the CPU for up to 65535 microseconds.
* Use the 250KHz MACA clock for longer delays to avoid interrupt effects.
* However that can't be used if the radio is being power cycled!
@ -118,7 +118,7 @@ clock_delay_usec(uint16_t howlong)
while(--i);
}
/*---------------------------------------------------------------------------*/
/**
/*
* Delay the CPU for up to 65535 milliseconds. The watchdog is NOT disabled.
*/
void
@ -127,7 +127,7 @@ clock_delay_msec(uint16_t howlong)
while(howlong--) clock_delay_usec(1000);
}
/*---------------------------------------------------------------------------*/
/**
/*
* Legacy delay. The original clock_delay for the msp430 used a granularity
* of 2.83 usec. This approximates that delay for values up to 1456 usec.
* (The largest core call in leds.c uses 400).
@ -139,7 +139,7 @@ clock_delay(unsigned int howlong)
clock_delay_usec((283*howlong)/100);
}
/*---------------------------------------------------------------------------*/
/**
/*
* Adjust clock ticks after a cpu sleep.
*/
void clock_adjust_ticks(clock_time_t howmany) {

2
cpu/msp430/f1xxx/clock.c
View file

@ -195,7 +195,7 @@ clock_delay(unsigned int i)
}
}
/*---------------------------------------------------------------------------*/
/**
/*
* Wait for a multiple of 10 ms.
*
*/

2
cpu/msp430/f5xxx/clock.c
View file

@ -192,7 +192,7 @@ clock_delay(unsigned int i)
}
}
/*---------------------------------------------------------------------------*/
/**
/*
* Wait for a multiple of 10 ms.
*
*/

2
cpu/stm32w108/clock.c
View file

@ -113,7 +113,7 @@ clock_delay(unsigned int i)
}
}
/*---------------------------------------------------------------------------*/
/**
/*
* Wait for a multiple of 1 ms.
*/
void