cc2538: Clean up port and pin definitions

Homogenize port and pin definitions naming:
 - PERIPHERAL_FUNCTION_PORT for the port ID,
 - PERIPHERAL_FUNCTION_PIN for the pin ID,
 - PERIPHERAL_FUNCTION_PORT_BASE for the port base,
 - PERIPHERAL_FUNCTION_PIN_MASK for the pin mask.

Define only PERIPHERAL_FUNCTION_PORT and PERIPHERAL_FUNCTION_PIN in board.h, and
deduce PERIPHERAL_FUNCTION_PORT_BASE and PERIPHERAL_FUNCTION_PIN_MASK in the
driver from the former definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau 2013-11-25 15:00:41 +01:00
parent acee82abbb
commit d2f3795a30
5 changed files with 88 additions and 65 deletions

View file

@ -42,6 +42,15 @@
#include "dev/ssi.h"
#include "dev/gpio.h"
#define SPI_CLK_PORT_BASE GPIO_PORT_TO_BASE(SPI_CLK_PORT)
#define SPI_CLK_PIN_MASK GPIO_PIN_MASK(SPI_CLK_PIN)
#define SPI_MOSI_PORT_BASE GPIO_PORT_TO_BASE(SPI_MOSI_PORT)
#define SPI_MOSI_PIN_MASK GPIO_PIN_MASK(SPI_MOSI_PIN)
#define SPI_MISO_PORT_BASE GPIO_PORT_TO_BASE(SPI_MISO_PORT)
#define SPI_MISO_PIN_MASK GPIO_PIN_MASK(SPI_MISO_PIN)
#define SPI_SEL_PORT_BASE GPIO_PORT_TO_BASE(SPI_SEL_PORT)
#define SPI_SEL_PIN_MASK GPIO_PIN_MASK(SPI_SEL_PIN)
/* Default: Motorola mode 3 with 8-bit data words */
#ifndef SPI_CONF_PHASE
#define SPI_CONF_PHASE SSI_CR0_SPH
@ -61,10 +70,10 @@
* \brief Initialize the SPI bus.
*
* This SPI init() function uses the following #defines to set the pins:
* CC2538_SPI_CLK_PORT_NUM CC2538_SPI_CLK_PIN_NUM
* CC2538_SPI_MOSI_PORT_NUM CC2538_SPI_MOSI_PIN_NUM
* CC2538_SPI_MISO_PORT_NUM CC2538_SPI_MISO_PIN_NUM
* CC2538_SPI_SEL_PORT_NUM CC2538_SPI_SEL_PIN_NUM
* SPI_CLK_PORT SPI_CLK_PIN
* SPI_MOSI_PORT SPI_MOSI_PIN
* SPI_MISO_PORT SPI_MISO_PIN
* SPI_SEL_PORT SPI_SEL_PIN
*
* This sets the mode to Motorola SPI with the following format options:
* SPI_CONF_PHASE: 0 or SSI_CR0_SPH
@ -83,22 +92,22 @@ spi_init(void)
REG(SSI0_BASE + SSI_CC) = 1;
/* Set the mux correctly to connect the SSI pins to the correct GPIO pins */
ioc_set_sel(CC2538_SPI_CLK_PORT_NUM, CC2538_SPI_CLK_PIN_NUM, IOC_PXX_SEL_SSI0_CLKOUT);
ioc_set_sel(CC2538_SPI_MOSI_PORT_NUM, CC2538_SPI_MOSI_PIN_NUM, IOC_PXX_SEL_SSI0_TXD);
REG(IOC_SSIRXD_SSI0) = (CC2538_SPI_MISO_PORT_NUM * 8) + CC2538_SPI_MISO_PIN_NUM;
ioc_set_sel(CC2538_SPI_SEL_PORT_NUM, CC2538_SPI_SEL_PIN_NUM, IOC_PXX_SEL_SSI0_FSSOUT);
ioc_set_sel(SPI_CLK_PORT, SPI_CLK_PIN, IOC_PXX_SEL_SSI0_CLKOUT);
ioc_set_sel(SPI_MOSI_PORT, SPI_MOSI_PIN, IOC_PXX_SEL_SSI0_TXD);
REG(IOC_SSIRXD_SSI0) = (SPI_MISO_PORT * 8) + SPI_MISO_PIN;
ioc_set_sel(SPI_SEL_PORT, SPI_SEL_PIN, IOC_PXX_SEL_SSI0_FSSOUT);
/* Put all the SSI gpios into peripheral mode */
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(CC2538_SPI_CLK_PORT_NUM), GPIO_PIN_MASK(CC2538_SPI_CLK_PIN_NUM));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(CC2538_SPI_MOSI_PORT_NUM), GPIO_PIN_MASK(CC2538_SPI_MOSI_PIN_NUM));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(CC2538_SPI_MISO_PORT_NUM), GPIO_PIN_MASK(CC2538_SPI_MISO_PIN_NUM));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(CC2538_SPI_SEL_PORT_NUM), GPIO_PIN_MASK(CC2538_SPI_SEL_PIN_NUM));
GPIO_PERIPHERAL_CONTROL(SPI_CLK_PORT_BASE, SPI_CLK_PIN_MASK);
GPIO_PERIPHERAL_CONTROL(SPI_MOSI_PORT_BASE, SPI_MOSI_PIN_MASK);
GPIO_PERIPHERAL_CONTROL(SPI_MISO_PORT_BASE, SPI_MISO_PIN_MASK);
GPIO_PERIPHERAL_CONTROL(SPI_SEL_PORT_BASE, SPI_SEL_PIN_MASK);
/* Disable any pull ups or the like */
ioc_set_over(CC2538_SPI_CLK_PORT_NUM, CC2538_SPI_CLK_PIN_NUM, IOC_OVERRIDE_DIS);
ioc_set_over(CC2538_SPI_MOSI_PORT_NUM, CC2538_SPI_MOSI_PIN_NUM, IOC_OVERRIDE_DIS);
ioc_set_over(CC2538_SPI_MISO_PORT_NUM, CC2538_SPI_MISO_PIN_NUM, IOC_OVERRIDE_DIS);
ioc_set_over(CC2538_SPI_SEL_PORT_NUM, CC2538_SPI_SEL_PIN_NUM, IOC_OVERRIDE_DIS);
ioc_set_over(SPI_CLK_PORT, SPI_CLK_PIN, IOC_OVERRIDE_DIS);
ioc_set_over(SPI_MOSI_PORT, SPI_MOSI_PIN, IOC_OVERRIDE_DIS);
ioc_set_over(SPI_MISO_PORT, SPI_MISO_PIN, IOC_OVERRIDE_DIS);
ioc_set_over(SPI_SEL_PORT, SPI_SEL_PIN, IOC_OVERRIDE_DIS);
/* Configure the clock */
REG(SSI0_BASE + SSI_CPSR) = 2;

View file

@ -50,6 +50,18 @@
static int (* input_handler)(unsigned char c);
/*---------------------------------------------------------------------------*/
#define UART_RX_PORT_BASE GPIO_PORT_TO_BASE(UART_RX_PORT)
#define UART_RX_PIN_MASK GPIO_PIN_MASK(UART_RX_PIN)
#define UART_TX_PORT_BASE GPIO_PORT_TO_BASE(UART_TX_PORT)
#define UART_TX_PIN_MASK GPIO_PIN_MASK(UART_TX_PIN)
#define UART_CTS_PORT_BASE GPIO_PORT_TO_BASE(UART_CTS_PORT)
#define UART_CTS_PIN_MASK GPIO_PIN_MASK(UART_CTS_PIN)
#define UART_RTS_PORT_BASE GPIO_PORT_TO_BASE(UART_RTS_PORT)
#define UART_RTS_PIN_MASK GPIO_PIN_MASK(UART_RTS_PIN)
/*---------------------------------------------------------------------------*/
/*
* Once we know what UART we're on, configure correct values to be written to
* the correct registers
@ -138,8 +150,8 @@ uart_init(void)
ioc_set_over(UART_TX_PORT, UART_TX_PIN, IOC_OVERRIDE_OE);
/* Set RX and TX pins to peripheral mode */
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(UART_TX_PORT), GPIO_PIN_MASK(UART_TX_PIN));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(UART_RX_PORT), GPIO_PIN_MASK(UART_RX_PIN));
GPIO_PERIPHERAL_CONTROL(UART_TX_PORT_BASE, UART_TX_PIN_MASK);
GPIO_PERIPHERAL_CONTROL(UART_RX_PORT_BASE, UART_RX_PIN_MASK);
/*
* UART Interrupt Masks:

View file

@ -54,6 +54,9 @@
#include <stdbool.h>
#include <stdint.h>
/*---------------------------------------------------------------------------*/
#define USB_PULLUP_PORT_BASE GPIO_PORT_TO_BASE(USB_PULLUP_PORT)
#define USB_PULLUP_PIN_MASK GPIO_PIN_MASK(USB_PULLUP_PIN)
/*---------------------------------------------------------------------------*/
/* EP max FIFO sizes without double buffering */
#if CTRL_EP_SIZE > 32
#error Control endpoint size too big
@ -330,8 +333,8 @@ usb_arch_setup(void)
while(!(REG(USB_CTRL) & USB_CTRL_PLL_LOCKED));
/* Enable pull-up on usb port */
GPIO_SET_OUTPUT(USB_PULLUP_PORT, USB_PULLUP_PIN_MASK);
GPIO_SET_PIN(USB_PULLUP_PORT, USB_PULLUP_PIN_MASK);
GPIO_SET_OUTPUT(USB_PULLUP_PORT_BASE, USB_PULLUP_PIN_MASK);
GPIO_SET_PIN(USB_PULLUP_PORT_BASE, USB_PULLUP_PIN_MASK);
for(i = 0; i < USB_MAX_ENDPOINTS; i++) {
usb_endpoints[i].flags = 0;