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* Added f2xxx for two series (for example z1)

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* f1xxx is baseline and always included
* Cleaned up the names of uart and spi (no x in names)
* Updated SPI configuration for WiSMote
This commit is contained in:
Niclas Finne 2011-10-06 14:05:57 +02:00
parent 1a761ec3eb
commit cdfa8708e3
15 changed files with 289 additions and 204 deletions
Download patch file Download diff file Expand all files Collapse all files

8
cpu/msp430/Makefile.msp430
View file

@ -12,11 +12,15 @@ CONTIKI_CPU=$(CONTIKI)/cpu/msp430
### Define the source files we have in the MSP430 port
ifneq (,$(findstring msp430x5,$(MCU)))
CONTIKI_CPU_DIRS = ${addprefix f5xxx/,. dev} . dev
CONTIKI_CPU_FAM_DIR = f5xxx
else
CONTIKI_CPU_DIRS = ${addprefix f1xxx/,. dev} . dev
ifneq (,$(findstring msp430x2,$(MCU)))
CONTIKI_CPU_FAM_DIR = f2xxx
endif
endif
CONTIKI_CPU_DIRS = $(CONTIKI_CPU_FAM_DIR) f1xxx . dev
MSP430 = msp430.c flash.c clock.c leds.c leds-arch.c \
watchdog.c lpm.c mtarch.c rtimer-arch.c
UIPDRIVERS = me.c me_tabs.c slip.c crc16.c

2
cpu/msp430/f1xxx/clock.c
View file

@ -182,7 +182,7 @@ void
clock_delay(unsigned int i)
{
while(i--) {
asm("nop");
_NOP();
}
}
/*---------------------------------------------------------------------------*/

86
cpu/msp430/dev/uart1.c → cpu/msp430/f1xxx/uart1.c
View file

@ -92,11 +92,7 @@ handle_rxdma_timer(void *ptr)
uint8_t
uart1_active(void)
{
#if CONTIKI_TARGET_WISMOTE
return rx_in_progress | transmitting;
#else
return ((~ UTCTL1) & TXEPT) | rx_in_progress | transmitting;
#endif
}
/*---------------------------------------------------------------------------*/
void
@ -126,21 +122,16 @@ uart1_writeb(unsigned char c)
/* Loop until the transmission buffer is available. */
/*while((IFG2 & UTXIFG1) == 0);*/
UCA1TXBUF = ringbuf_get(&txbuf);
TXBUF1 = ringbuf_get(&txbuf);
}
#else /* TX_WITH_INTERRUPT */
#if CONTIKI_TARGET_WISMOTE
while(!(UCA1IFG & UCTXIFG)); // USCI_A1 TX buffer ready?
UCA1TXBUF = c;
#else
/* Loop until the transmission buffer is available. */
while((IFG2 & UTXIFG1) == 0);
/* Transmit the data. */
TXBUF1 = c;
#endif
#endif /* TX_WITH_INTERRUPT */
}
/*---------------------------------------------------------------------------*/
@ -151,35 +142,6 @@ uart1_writeb(unsigned char c)
void
uart1_init(unsigned long ubr)
{
#if CONTIKI_TARGET_WISMOTE
P4DIR |= BIT5;
P4OUT |= BIT5 ;
P5SEL |= BIT6|BIT7; // P5.6,7 = USCI_A1 TXD/RXD
P4SEL |= BIT7;
P4DIR |= BIT7;
UCA1CTL1 |= UCSWRST; // **Put state machine in reset**
UCA1CTL1 |= UCSSEL_2; // SMCLK
UCA1BR0 = 139;//69; // Baudrate 57600 (see User's Guide)
UCA1BR1 = 0; //
UCA1MCTL |= UCBRS_2 + UCBRF_0; // Modulation UCBRFx=0
UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA1IE |= UCRXIE;
UCA1IFG &= ~UCRXIFG;
//UCA1IFG &= ~UCTXIFG;
// UCA1TCTL1 |= URXSE;
rx_in_progress = 0;
transmitting = 0;
#if TX_WITH_INTERRUPT
ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data));
UCA1IE |= UCTXIE;
//UCA1IFG &= ~UCTXIFG;
#endif /* TX_WITH_INTERRUPT */
#else
/* RS232 */
P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
@ -271,53 +233,8 @@ uart1_init(unsigned long ubr)
msp430_add_lpm_req(MSP430_REQUIRE_LPM1);
#endif /* RX_WITH_DMA */
#endif
}
/*---------------------------------------------------------------------------*/
#if CONTIKI_TARGET_WISMOTE
#ifdef __IAR_SYSTEMS_ICC__
#pragma vector=USCI_A1_VECTOR
__interrupt void
#else
interrupt(USCI_A1_VECTOR)
#endif
uart1_rx_interrupt(void)
{
uint8_t c;
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if(UCRXIFG & UCA1IFG) {
rx_in_progress = 0;
// Check status register for receive errors.
if(UCA1STAT & UCRXERR) {
c = UCA1RXBUF; // Clear error flags by forcing a dummy read.
} else {
c = UCA1RXBUF;
if(uart1_input_handler != NULL) {
if(uart1_input_handler(c)) {
LPM4_EXIT;
}
}
}
UCA1IFG &= ~UCRXIFG;
}
#if TX_WITH_INTERRUPT
if(UCTXIFG & UCA1IFG) {
if(ringbuf_elements(&txbuf) == 0) {
transmitting = 0;
} else {
UCA1TXBUF = ringbuf_get(&txbuf);
}
UCA1IFG &= ~UCTXIFG;
}
#endif
//UCA1IFG &= 0x00;
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
#else
#if !RX_WITH_DMA
#ifdef __IAR_SYSTEMS_ICC__
#pragma vector=UART1RX_VECTOR
@ -375,5 +292,4 @@ uart1_tx_interrupt(void)
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
#endif /* TX_WITH_INTERRUPT */
#endif
/*---------------------------------------------------------------------------*/

9
cpu/msp430/f1xxx/spix.c → cpu/msp430/f2xxx/spi.c
View file

@ -25,8 +25,6 @@
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)$Id: spix.c,v 1.1 2010/08/24 16:23:20 joxe Exp $
*/
#include "contiki.h"
@ -43,12 +41,7 @@ unsigned char spi_busy = 0;
void
spi_init(void)
{
//static unsigned char spi_inited = 0;
//if (spi_inited)
//return;
// Initalize ports for communication with SPI units.
// Initialize ports for communication with SPI units.
UCB0CTL1 |= UCSWRST; //reset usci
UCB0CTL1 |= UCSSEL_2; //smclk while usci is reset

0
cpu/msp430/dev/uart0x.c → cpu/msp430/f2xxx/uart0.c
View file

0
cpu/msp430/dev/uart1x.c → cpu/msp430/f2xxx/uart1.c
View file

2
cpu/msp430/f5xxx/clock.c
View file

@ -179,7 +179,7 @@ void
clock_delay(unsigned int i)
{
while(i--) {
asm("nop");
_NOP();
}
}
/*---------------------------------------------------------------------------*/

0
cpu/msp430/f5xxx/spix.c → cpu/msp430/f5xxx/spi.c
View file

126
cpu/msp430/f5xxx/uart0.c Normal file
View file

@ -0,0 +1,126 @@
/*
* Copyright (c) 2011, Swedish Institute of Computer Science
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Yet another machine dependent MSP430X UART0 code.
* IF2, etc. can not be used here... need to abstract to some macros
* later.
*/
#include "contiki.h"
#include <stdlib.h>
#include "sys/energest.h"
#include "dev/uart0.h"
#include "dev/watchdog.h"
static int (*uart0_input_handler)(unsigned char c);
static volatile uint8_t transmitting;
/*---------------------------------------------------------------------------*/
uint8_t
uart0_active(void)
{
return (UCA0STAT & UCBUSY) | transmitting;
}
/*---------------------------------------------------------------------------*/
void
uart0_set_input(int (*input)(unsigned char c))
{
uart0_input_handler = input;
}
/*---------------------------------------------------------------------------*/
void
uart0_writeb(unsigned char c)
{
watchdog_periodic();
/* Loop until the transmission buffer is available. */
while((UCA0STAT & UCBUSY));
/* Transmit the data. */
UCA0TXBUF = c;
}
/*---------------------------------------------------------------------------*/
/**
* Initalize the RS232 port.
*
*/
void
uart0_init(unsigned long ubr)
{
/* RS232 */
UCA0CTL1 |= UCSWRST; /* Hold peripheral in reset state */
UCA0CTL1 |= UCSSEL_2; /* CLK = SMCLK */
ubr = (MSP430_CPU_SPEED / ubr);
UCA0BR0 = ubr & 0xff;
UCA0BR1 = (ubr >> 8) & 0xff;
UCA0MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
P3DIR &= ~0x20; /* P3.5 = USCI_A0 RXD as input */
P3DIR |= 0x10; /* P3.4 = USCI_A0 TXD as output */
P3SEL |= 0x30; /* P3.4,5 = USCI_A0 TXD/RXD */
/*UCA0CTL1 &= ~UCSWRST;*/ /* Initialize USCI state machine */
transmitting = 0;
/* XXX Clear pending interrupts before enable */
UCA0IE &= ~UCRXIFG;
UCA0IE &= ~UCTXIFG;
UCA0CTL1 &= ~UCSWRST; /* Initialize USCI state machine **before** enabling interrupts */
UCA0IE |= UCRXIE; /* Enable UCA0 RX interrupt */
}
/*---------------------------------------------------------------------------*/
#ifdef __IAR_SYSTEMS_ICC__
#pragma vector=USCI_A0_VECTOR
__interrupt void
#else
interrupt(USCI_A0_VECTOR)
#endif
uart0_rx_interrupt(void)
{
uint8_t c;
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if (UCA0IV == 2) {
if(UCA0STAT & UCRXERR) {
c = UCA0RXBUF; /* Clear error flags by forcing a dummy read. */
} else {
c = UCA0RXBUF;
if(uart0_input_handler != NULL) {
if(uart0_input_handler(c)) {
LPM4_EXIT;
}
}
}
}
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/

131
cpu/msp430/f5xxx/uart1.c Normal file
View file

@ -0,0 +1,131 @@
/*
* Copyright (c) 2011, Swedish Institute of Computer Science
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Yet another machine dependent MSP430X UART0 code.
* IF2, etc. can not be used here... need to abstract to some macros
* later.
*/
#include "contiki.h"
#include <stdlib.h>
#include "sys/energest.h"
#include "dev/uart1.h"
#include "dev/watchdog.h"
static int (*uart1_input_handler)(unsigned char c);
static volatile uint8_t transmitting;
/*---------------------------------------------------------------------------*/
uint8_t
uart1_active(void)
{
return (UCA1STAT & UCBUSY) | transmitting;
}
/*---------------------------------------------------------------------------*/
void
uart1_set_input(int (*input)(unsigned char c))
{
uart1_input_handler = input;
}
/*---------------------------------------------------------------------------*/
void
uart1_writeb(unsigned char c)
{
watchdog_periodic();
/* Loop until the transmission buffer is available. */
while((UCA1STAT & UCBUSY));
/* Transmit the data. */
UCA1TXBUF = c;
}
/*---------------------------------------------------------------------------*/
/**
* Initalize the RS232 port.
*
*/
void
uart1_init(unsigned long ubr)
{
/* RS232 */
UCA1CTL1 |= UCSWRST; /* Hold peripheral in reset state */
UCA1CTL1 |= UCSSEL_2; /* CLK = SMCLK */
ubr = (MSP430_CPU_SPEED / ubr);
UCA1BR0 = ubr & 0xff;
UCA1BR1 = (ubr >> 8) & 0xff;
/* UCA1MCTL |= UCBRS_2 + UCBRF_0; // Modulation UCBRFx=0 */
UCA1MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
P4DIR |= BIT5;
P4OUT |= BIT5 ;
P5SEL |= BIT6|BIT7; // P5.6,7 = USCI_A1 TXD/RXD
P4SEL |= BIT7;
P4DIR |= BIT7;
/*UCA1CTL1 &= ~UCSWRST;*/ /* Initialize USCI state machine */
transmitting = 0;
/* XXX Clear pending interrupts before enable */
UCA1IE &= ~UCRXIFG;
UCA1IE &= ~UCTXIFG;
UCA1CTL1 &= ~UCSWRST; /* Initialize USCI state machine **before** enabling interrupts */
UCA1IE |= UCRXIE; /* Enable UCA1 RX interrupt */
}
/*---------------------------------------------------------------------------*/
#ifdef __IAR_SYSTEMS_ICC__
#pragma vector=USCI_A1_VECTOR
__interrupt void
#else
interrupt(USCI_A1_VECTOR)
#endif
uart1_rx_interrupt(void)
{
uint8_t c;
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if (UCA1IV == 2) {
if(UCA1STAT & UCRXERR) {
c = UCA1RXBUF; /* Clear error flags by forcing a dummy read. */
} else {
c = UCA1RXBUF;
if(uart1_input_handler != NULL) {
if(uart1_input_handler(c)) {
LPM4_EXIT;
}
}
}
}
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/