Fix the uart0 flow control register P0SEL setting in cpu cc253x

2015-01-25 13:57:40 +08:00 · 2015-01-25 13:57:40 +08:00 · cd4322cec2
parent 6fb7dd238e
commit cd4322cec2
1 changed files with 1 additions and 1 deletions
--- a/cpu/cc253x/dev/uart0.c
+++ b/cpu/cc253x/dev/uart0.c
@ -39,7 +39,7 @@ uart0_init()
 #else
  PERCFG &= ~PERCFG_U0CFG; /* alternative port 1 = P0.5-2 */
 #ifdef UART0_RTSCTS
-  P0SEL |= 0x20 | 0x10;    /* peripheral select for TX and RX */
+  P0SEL |= 0x3C;    /* peripheral select for RTS and CTS, TX, RX */
 #else
  P0SEL |= 0x0C;    /* peripheral select for TX and RX */
  P0 &= ~0x20;    /* RTS down */