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Update cpu files to reflect API in latest CCxxware versions

master-31012017
George Oikonomou 2016-06-11 19:40:14 +01:00
parent 0e4c02bf3b
commit ccba6bdb20
6 changed files with 28 additions and 28 deletions
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6
cpu/cc26xx-cc13xx/dev/cc26xx-uart.c
View File

@ -120,7 +120,7 @@ static void
disable_interrupts(void)
{
/* Acknowledge UART interrupts */
ti_lib_int_disable(INT_UART0);
ti_lib_int_disable(INT_UART0_COMB);
/* Disable all UART module interrupts */
ti_lib_uart_int_disable(UART0_BASE, CC26XX_UART_INTERRUPT_ALL);
@ -141,7 +141,7 @@ enable_interrupts(void)
ti_lib_uart_int_enable(UART0_BASE, CC26XX_UART_RX_INTERRUPT_TRIGGERS);
/* Acknowledge UART interrupts */
ti_lib_int_enable(INT_UART0);
ti_lib_int_enable(INT_UART0_COMB);
}
}
/*---------------------------------------------------------------------------*/
@ -154,7 +154,7 @@ configure(void)
* to avoid falling edge glitches
*/
ti_lib_ioc_pin_type_gpio_output(BOARD_IOID_UART_TX);
ti_lib_gpio_pin_write(BOARD_UART_TX, 1);
ti_lib_gpio_set_dio(BOARD_IOID_UART_TX);
/*
* Map UART signals to the correct GPIO pins and configure them as

8
cpu/cc26xx-cc13xx/dev/gpio-interrupt.c
View File

@ -55,7 +55,7 @@ gpio_interrupt_register_handler(uint8_t ioid, gpio_interrupt_handler_t f)
uint8_t interrupts_disabled = ti_lib_int_master_disable();
/* Clear interrupts on specified pins */
ti_lib_gpio_event_clear(1 << ioid);
ti_lib_gpio_clear_event_dio(ioid);
handlers[ioid] = f;
@ -74,7 +74,7 @@ gpio_interrupt_init()
handlers[i] = NULL;
}
ti_lib_int_enable(INT_EDGE_DETECT);
ti_lib_int_enable(INT_AON_GPIO_EDGE);
}
/*---------------------------------------------------------------------------*/
void
@ -86,13 +86,13 @@ gpio_interrupt_isr(void)
ENERGEST_ON(ENERGEST_TYPE_IRQ);
/* Read interrupt flags */
pin_mask = (HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) & GPIO_PIN_MASK);
pin_mask = (HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) & GPIO_DIO_ALL_MASK);
/* Clear the interrupt flags */
HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = pin_mask;
/* Run custom ISRs */
for(i = 0; i < NUM_GPIO_PINS; i++) {
for(i = 0; i < NUM_IO_MAX; i++) {
/* Call the handler if there is one registered for this event */
if((pin_mask & (1 << i)) && handlers[i] != NULL) {
handlers[i](i);

2
cpu/cc26xx-cc13xx/dev/soc-rtc.c
View File

@ -100,7 +100,7 @@ soc_rtc_init(void)
ti_lib_aon_rtc_channel_enable(AON_RTC_CH1);
ti_lib_aon_rtc_enable();
ti_lib_int_enable(INT_AON_RTC);
ti_lib_rom_int_enable(INT_AON_RTC_COMB);
/* Re-enable interrupts */
if(!interrupts_disabled) {

4
cpu/cc26xx-cc13xx/dev/soc-trng.c
View File

@ -71,7 +71,7 @@ static void
disable_number_ready_interrupt(void)
{
ti_lib_trng_int_disable(TRNG_NUMBER_READY);
ti_lib_rom_int_disable(INT_TRNG);
ti_lib_rom_int_disable(INT_TRNG_IRQ);
}
/*---------------------------------------------------------------------------*/
static void
@ -79,7 +79,7 @@ enable_number_ready_interrupt(void)
{
ti_lib_trng_int_clear(TRNG_NUMBER_READY);
ti_lib_trng_int_enable(TRNG_NUMBER_READY);
ti_lib_rom_int_enable(INT_TRNG);
ti_lib_rom_int_enable(INT_TRNG_IRQ);
}
/*---------------------------------------------------------------------------*/
static bool

4
cpu/cc26xx-cc13xx/lpm.c
View File

@ -127,7 +127,7 @@ lpm_shutdown(uint32_t wakeup_pin, uint32_t io_pull, uint32_t wake_on)
/* Configure the wakeup trigger */
if(wakeup_pin != IOID_UNUSED) {
ti_lib_gpio_dir_mode_set((1 << wakeup_pin), GPIO_DIR_MODE_IN);
ti_lib_gpio_set_output_enable_dio(wakeup_pin, GPIO_OUTPUT_DISABLE);
ti_lib_ioc_port_configure_set(wakeup_pin, IOC_PORT_GPIO, io_cfg);
}
@ -584,7 +584,7 @@ lpm_pin_set_default_state(uint32_t ioid)
}
ti_lib_ioc_port_configure_set(ioid, IOC_PORT_GPIO, IOC_STD_OUTPUT);
ti_lib_gpio_dir_mode_set((1 << ioid), GPIO_DIR_MODE_IN);
ti_lib_gpio_set_output_enable_dio(ioid, GPIO_OUTPUT_DISABLE);
}
/*---------------------------------------------------------------------------*/
/**

32
cpu/cc26xx-cc13xx/rf-core/rf-core.c
View File

@ -236,10 +236,10 @@ rf_core_power_up()
uint32_t cmd_status;
bool interrupts_disabled = ti_lib_int_master_disable();
ti_lib_int_pend_clear(INT_RF_CPE0);
ti_lib_int_pend_clear(INT_RF_CPE1);
ti_lib_int_disable(INT_RF_CPE0);
ti_lib_int_disable(INT_RF_CPE1);
ti_lib_int_pend_clear(INT_RFC_CPE_0);
ti_lib_int_pend_clear(INT_RFC_CPE_1);
ti_lib_int_disable(INT_RFC_CPE_0);
ti_lib_int_disable(INT_RFC_CPE_1);
/* Enable RF Core power domain */
ti_lib_prcm_power_domain_on(PRCM_DOMAIN_RFCORE);
@ -252,8 +252,8 @@ rf_core_power_up()
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = 0x0;
ti_lib_int_enable(INT_RF_CPE0);
ti_lib_int_enable(INT_RF_CPE1);
ti_lib_int_enable(INT_RFC_CPE_0);
ti_lib_int_enable(INT_RFC_CPE_1);
if(!interrupts_disabled) {
ti_lib_int_master_enable();
@ -335,8 +335,8 @@ void
rf_core_power_down()
{
bool interrupts_disabled = ti_lib_int_master_disable();
ti_lib_int_disable(INT_RF_CPE0);
ti_lib_int_disable(INT_RF_CPE1);
ti_lib_int_disable(INT_RFC_CPE_0);
ti_lib_int_disable(INT_RFC_CPE_1);
if(rf_core_is_accessible()) {
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
@ -358,10 +358,10 @@ rf_core_power_down()
while(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_RFCORE)
!= PRCM_DOMAIN_POWER_OFF);
ti_lib_int_pend_clear(INT_RF_CPE0);
ti_lib_int_pend_clear(INT_RF_CPE1);
ti_lib_int_enable(INT_RF_CPE0);
ti_lib_int_enable(INT_RF_CPE1);
ti_lib_int_pend_clear(INT_RFC_CPE_0);
ti_lib_int_pend_clear(INT_RFC_CPE_1);
ti_lib_int_enable(INT_RFC_CPE_0);
ti_lib_int_enable(INT_RFC_CPE_1);
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
@ -462,10 +462,10 @@ rf_core_setup_interrupts(bool poll_mode)
/* Clear interrupt flags, active low clear(?) */
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
ti_lib_int_pend_clear(INT_RF_CPE0);
ti_lib_int_pend_clear(INT_RF_CPE1);
ti_lib_int_enable(INT_RF_CPE0);
ti_lib_int_enable(INT_RF_CPE1);
ti_lib_int_pend_clear(INT_RFC_CPE_0);
ti_lib_int_pend_clear(INT_RFC_CPE_1);
ti_lib_int_enable(INT_RFC_CPE_0);
ti_lib_int_enable(INT_RFC_CPE_1);
if(!interrupts_disabled) {
ti_lib_int_master_enable();