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Import of the contiki-2.x development code from the SICS internal CVS server

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adamdunkels 2006-06-17 22:41:10 +00:00
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/*
* Copyright (c) 2005, Swedish Institute of Computer Science
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the Contiki operating system.
*
* @(#)$Id: msp430.c,v 1.1 2006/06/17 22:41:21 adamdunkels Exp $
*/
#include <io.h>
#include <signal.h>
#include "net/uip.h"
/*---------------------------------------------------------------------------*/
void
msp430_init_dco(void)
{
/* This code taken from the FU Berlin sources and reformatted. */
#define DELTA 600
unsigned int compare, oldcapture = 0;
unsigned int i;
BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
and SSMCLK. XT2 is off. */
BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
crystal DCO frquenzy = 2,4576 MHz */
WDTCTL = WDTPW + WDTHOLD; /* Stop WDT */
BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
for(i = 0xffff; i > 0; i--); /* Delay for XTAL to settle */
CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
while(1) {
while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
compare = CCR2; /* Get current captured SMCLK */
compare = compare - oldcapture; /* SMCLK difference */
oldcapture = CCR2; /* Save current captured SMCLK */
if(DELTA == compare) {
break; /* if equal, leave "while(1)" */
} else if(DELTA < compare) { /* DCO is too fast, slow it down */
DCOCTL--;
if(DCOCTL == 0xFF) { /* Did DCO role under? */
BCSCTL1--;
}
} else { /* -> Select next lower RSEL */
DCOCTL++;
if(DCOCTL == 0x00) { /* Did DCO role over? */
BCSCTL1++;
}
/* -> Select next higher RSEL */
}
}
CCTL2 = 0; /* Stop CCR2 function */
TACTL = 0; /* Stop Timer_A */
BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
}
/*---------------------------------------------------------------------------*/
static void
init_ports(void)
{
/* Turn everything off, device drivers are supposed to enable what is
* really needed!
*/
/* All configured for digital I/O */
#ifdef P1SEL
P1SEL = 0;
#endif
#ifdef P2SEL
P2SEL = 0;
#endif
#ifdef P3SEL
P3SEL = 0;
#endif
#ifdef P4SEL
P4SEL = 0;
#endif
#ifdef P5SEL
P5SEL = 0;
#endif
#ifdef P6SEL
P6SEL = 0;
#endif
/* All available inputs */
#ifdef P1DIR
P1DIR = 0;
P1OUT = 0;
#endif
#ifdef P2DIR
P2DIR = 0;
P2OUT = 0;
#endif
#ifdef P3DIR
P3DIR = 0;
P3OUT = 0;
#endif
#ifdef P4DIR
P4DIR = 0;
P4OUT = 0;
#endif
#ifdef P5DIR
P5DIR = 0;
P5OUT = 0;
#endif
#ifdef P6DIR
P6DIR = 0;
P6OUT = 0;
#endif
P1IE = 0;
P2IE = 0;
}
/*---------------------------------------------------------------------------*/
void
msp430_cpu_init(void)
{
dint();
init_ports();
msp430_init_dco();
eint();
}
#define asmv(arg) __asm__ __volatile__(arg)
/*
* Mask all interrupts that can be masked.
*/
int
splhigh_(void)
{
/* Clear the GIE (General Interrupt Enable) flag. */
int sr;
asmv("mov r2, %0" : "=r" (sr));
asmv("bic %0, r2" : : "i" (GIE));
return sr & GIE; /* Ignore other sr bits. */
}
/*
* Restore previous interrupt mask.
*/
void
splx_(int sr)
{
/* If GIE was set, restore it. */
asmv("bis %0, r2" : : "r" (sr));
}
#ifdef UIP_ARCH_IPCHKSUM
u16_t
uip_ipchksum(void)
{
/* Assumes proper alignement of uip_buf. */
u16_t *p = (u16_t *)&uip_buf[UIP_LLH_LEN];
register u16_t sum;
sum = p[0];
asmv("add %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[1]));
asmv("addc %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[2]));
asmv("addc %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[3]));
asmv("addc %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[4]));
asmv("addc %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[5]));
asmv("addc %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[6]));
asmv("addc %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[7]));
asmv("addc %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[8]));
asmv("addc %[p], %[sum]": [sum] "+r" (sum): [p] "m" (p[9]));
/* Finally, add the remaining carry bit. */
asmv("addc #0, %[sum]": [sum] "+r" (sum));
/* Return sum in network byte order. */
return (sum == 0) ? 0xffff : sum;
}
#endif