cc2538: aes: Add support for generic operations
Add generic AES functions that should be able to support all the modes of operation of the hardware AES crypto engine, i.e. ECB, CBC, CTR, CBC-MAC, GCM, and CCM. This makes it possible to easily implement these modes of operation without duplicating code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This commit is contained in:
Benoît Thébaudeau
parent
ca919ab0b0
commit
baef75752e
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@ -42,9 +42,11 @@
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*/
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#include "contiki.h"
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#include "dev/rom-util.h"
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#include "dev/nvic.h"
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#include "dev/aes.h"
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#include "reg.h"
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#include <stdbool.h>
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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uint8_t
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@ -53,7 +55,7 @@ aes_load_keys(const void *keys, uint8_t key_size, uint8_t count,
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{
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uint32_t aes_key_store_size;
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uint32_t areas;
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uint64_t aligned_keys[16];
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uint64_t aligned_keys[AES_KEY_AREAS * 128 / 8 / sizeof(uint64_t)];
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int i;
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if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
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@ -63,7 +65,8 @@ aes_load_keys(const void *keys, uint8_t key_size, uint8_t count,
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/* 192-bit keys must be padded to 256 bits */
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if(key_size == AES_KEY_STORE_SIZE_KEY_SIZE_192) {
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for(i = 0; i < count; i++) {
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rom_util_memcpy(&aligned_keys[i << 2], &((uint64_t *)keys)[i * 3], 24);
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rom_util_memcpy(&aligned_keys[i << 2], &((const uint64_t *)keys)[i * 3],
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192 / 8);
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aligned_keys[(i << 2) + 3] = 0;
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}
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}
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@ -148,5 +151,181 @@ aes_load_keys(const void *keys, uint8_t key_size, uint8_t count,
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return CRYPTO_SUCCESS;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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aes_auth_crypt_start(uint32_t ctrl, uint8_t key_area, const void *iv,
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const void *adata, uint16_t adata_len,
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const void *data_in, void *data_out, uint16_t data_len,
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struct process *process)
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{
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if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
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return CRYPTO_RESOURCE_IN_USE;
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}
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/* Workaround for AES registers not retained after PM2 */
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REG(AES_CTRL_INT_CFG) = AES_CTRL_INT_CFG_LEVEL;
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_DMA_IN_DONE |
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AES_CTRL_INT_EN_RESULT_AV;
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REG(AES_CTRL_ALG_SEL) = AES_CTRL_ALG_SEL_AES;
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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REG(AES_KEY_STORE_READ_AREA) = key_area;
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/* Wait until key is loaded to the AES module */
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while(REG(AES_KEY_STORE_READ_AREA) & AES_KEY_STORE_READ_AREA_BUSY);
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/* Check for Key Store read error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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/* Clear the Keystore Read error bit */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return AES_KEYSTORE_READ_ERROR;
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}
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if(iv != NULL) {
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/* Write initialization vector */
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REG(AES_AES_IV_0) = ((const uint32_t *)iv)[0];
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REG(AES_AES_IV_1) = ((const uint32_t *)iv)[1];
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REG(AES_AES_IV_2) = ((const uint32_t *)iv)[2];
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REG(AES_AES_IV_3) = ((const uint32_t *)iv)[3];
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}
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/* Program AES authentication/crypto operation */
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REG(AES_AES_CTRL) = ctrl;
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/* Write the length of the payload block (lo) */
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REG(AES_AES_C_LENGTH_0) = data_len;
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/* Write the length of the payload block (hi) */
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REG(AES_AES_C_LENGTH_1) = 0;
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/* For combined modes only (CCM or GCM) */
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if(ctrl & (AES_AES_CTRL_CCM | AES_AES_CTRL_GCM)) {
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/* Write the length of the AAD data block (may be non-block size-aligned) */
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REG(AES_AES_AUTH_LENGTH) = adata_len;
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if(adata_len != 0) {
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/* Configure DMAC to fetch the AAD data
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the AAD data buffer */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)adata;
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/* AAD data length in bytes */
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REG(AES_DMAC_CH0_DMALENGTH) = adata_len;
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/* Wait for completion of the AAD data transfer, DMA_IN_DONE */
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while(!(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_IN_DONE));
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/* Check for the absence of error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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/* Clear the DMA error */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return CRYPTO_DMA_BUS_ERROR;
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}
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}
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}
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/* Clear interrupt status */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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if(process != NULL) {
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crypto_register_process_notification(process);
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nvic_interrupt_unpend(NVIC_INT_AES);
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nvic_interrupt_enable(NVIC_INT_AES);
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}
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/* Enable result available bit in interrupt enable */
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_RESULT_AV;
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if(data_len != 0) {
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/* Configure DMAC
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the input payload data buffer */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)data_in;
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/* Input payload data length in bytes */
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REG(AES_DMAC_CH0_DMALENGTH) = data_len;
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if(data_out != NULL) {
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/* Enable DMA channel 1 */
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REG(AES_DMAC_CH1_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the output payload data buffer */
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REG(AES_DMAC_CH1_EXTADDR) = (uint32_t)data_out;
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/* Output payload data length in bytes */
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REG(AES_DMAC_CH1_DMALENGTH) = data_len;
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}
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}
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return CRYPTO_SUCCESS;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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aes_auth_crypt_check_status(void)
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{
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return !!(REG(AES_CTRL_INT_STAT) &
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(AES_CTRL_INT_STAT_DMA_BUS_ERR | AES_CTRL_INT_STAT_KEY_ST_WR_ERR |
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AES_CTRL_INT_STAT_KEY_ST_RD_ERR | AES_CTRL_INT_STAT_RESULT_AV));
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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aes_auth_crypt_get_result(void *iv, void *tag)
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{
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uint32_t aes_ctrl_int_stat;
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aes_ctrl_int_stat = REG(AES_CTRL_INT_STAT);
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/* Clear the error bits */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR |
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AES_CTRL_INT_CLR_KEY_ST_WR_ERR |
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AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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nvic_interrupt_disable(NVIC_INT_AES);
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crypto_register_process_notification(NULL);
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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return CRYPTO_DMA_BUS_ERROR;
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}
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_WR_ERR) {
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return AES_KEYSTORE_WRITE_ERROR;
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}
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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return AES_KEYSTORE_READ_ERROR;
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}
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if(iv != NULL || tag != NULL) {
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/* Read result
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* Wait for the context ready bit */
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while(!(REG(AES_AES_CTRL) & AES_AES_CTRL_SAVED_CONTEXT_READY));
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if(iv != NULL) {
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/* Read the initialization vector registers */
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((uint32_t *)iv)[0] = REG(AES_AES_IV_0);
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((uint32_t *)iv)[1] = REG(AES_AES_IV_1);
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((uint32_t *)iv)[2] = REG(AES_AES_IV_2);
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((uint32_t *)iv)[3] = REG(AES_AES_IV_3);
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}
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if(tag != NULL) {
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/* Read the tag registers */
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((uint32_t *)tag)[0] = REG(AES_AES_TAG_OUT_0);
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((uint32_t *)tag)[1] = REG(AES_AES_TAG_OUT_1);
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((uint32_t *)tag)[2] = REG(AES_AES_TAG_OUT_2);
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((uint32_t *)tag)[3] = REG(AES_AES_TAG_OUT_3);
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}
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}
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/* Clear the interrupt status */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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return CRYPTO_SUCCESS;
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}
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/** @} */
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@ -51,6 +51,7 @@
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#include "contiki.h"
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#include "dev/crypto.h"
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#include <stdbool.h>
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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/** \name AES register offsets
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@ -464,6 +465,16 @@
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*/
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#define AES_KEYSTORE_READ_ERROR 5
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#define AES_KEYSTORE_WRITE_ERROR 6
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#define AES_AUTHENTICATION_FAILED 7
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES constants
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* @{
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*/
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#define AES_KEY_AREAS 8
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#define AES_BLOCK_LEN (128 / 8)
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#define AES_IV_LEN AES_BLOCK_LEN
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#define AES_TAG_LEN AES_BLOCK_LEN
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name AES functions
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@ -473,10 +484,11 @@
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/** \brief Writes keys into the Key RAM
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* \param keys Pointer to AES Keys
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* \param key_size Key size: \c AES_KEY_STORE_SIZE_KEY_SIZE_x
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* \param count Number of keys (1 to 8 - \p start_area for 128-bit keys, 1 to
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* (8 - \p start_area) / 2 for 192- and 256-bit keys)
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* \param start_area Start area in Key RAM where to store the key (0 to 7, must
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* be even for 192- and 256-bit keys)
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* \param count Number of keys (1 to \c AES_KEY_AREAS - \p start_area for
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* 128-bit keys, 1 to (\c AES_KEY_AREAS - \p start_area) / 2 for 192- and
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* 256-bit keys)
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* \param start_area Start area in Key RAM where to store the keys (0 to
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* \c AES_KEY_AREAS - 1, must be even for 192- and 256-bit keys)
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* \return \c CRYPTO_SUCCESS if successful, or CRYPTO/AES error code
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* \note Calling this function with a value of \p key_size different from the
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* one passed for the previous calls causes the deletion of all previously
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@ -485,6 +497,43 @@
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uint8_t aes_load_keys(const void *keys, uint8_t key_size, uint8_t count,
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uint8_t start_area);
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/** \brief Starts an AES authentication/crypto operation
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* \param ctrl Contents of the \c AES_AES_CTRL register
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* \param key_area Area in Key RAM where the key is stored (0 to
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* \c AES_KEY_AREAS - 1)
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* \param iv Pointer to 128-bit initialization vector, or \c NULL
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* \param adata Pointer to additional authenticated data in SRAM, or \c NULL
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* \param adata_len Length of additional authenticated data in octets, or \c 0
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* \param data_in Pointer to input payload data in SRAM, or \c NULL
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* \param data_out Pointer to output payload data in SRAM (may be \p data_in),
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* or \c NULL
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* \param data_len Length of payload data in octets, or \c 0
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* \param process Process to be polled upon completion of the operation, or
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* \c NULL
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* \return \c CRYPTO_SUCCESS if successful, or CRYPTO/AES error code
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* \note This function is only supposed to be called by the AES drivers.
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*/
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uint8_t aes_auth_crypt_start(uint32_t ctrl, uint8_t key_area, const void *iv,
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const void *adata, uint16_t adata_len,
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const void *data_in, void *data_out,
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uint16_t data_len, struct process *process);
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/** \brief Checks the status of the AES authentication/crypto operation
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* \retval false Result not yet available, and no error occurred
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* \retval true Result available, or error occurred
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* \note This function is only supposed to be called by the AES drivers.
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*/
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uint8_t aes_auth_crypt_check_status(void);
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/** \brief Gets the result of the AES authentication/crypto operation
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* \param iv Pointer to 128-bit result initialization vector, or \c NULL
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* \param tag Pointer to 128-bit result tag, or \c NULL
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* \return \c CRYPTO_SUCCESS if successful, or CRYPTO/AES error code
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* \note This function must be called only after \c aes_auth_crypt_start().
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* \note This function is only supposed to be called by the AES drivers.
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*/
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uint8_t aes_auth_crypt_get_result(void *iv, void *tag);
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/** @} */
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#endif /* AES_H_ */
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@ -43,49 +43,30 @@
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#include "contiki.h"
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#include "sys/cc.h"
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#include "dev/rom-util.h"
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#include "dev/nvic.h"
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#include "dev/ccm.h"
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#include "reg.h"
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#include <stdbool.h>
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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uint8_t
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ccm_auth_encrypt_start(uint8_t len_len, uint8_t key_area, const void *nonce,
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const void *adata, uint16_t adata_len, void *pdata,
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uint16_t pdata_len, uint8_t mic_len,
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struct process *process)
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static uint8_t
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ccm_auth_crypt_start(uint8_t encrypt, uint8_t len_len, uint8_t key_area,
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const void *nonce, const void *adata, uint16_t adata_len,
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void *data, uint16_t data_len, uint8_t mic_len,
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struct process *process)
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{
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uint32_t ctrl;
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uint32_t iv[4];
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if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
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return CRYPTO_RESOURCE_IN_USE;
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}
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/* Program AES-CCM authentication/crypto operation */
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ctrl = AES_AES_CTRL_SAVE_CONTEXT | /* Save context */
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(((MAX(mic_len, 2) - 2) >> 1) << AES_AES_CTRL_CCM_M_S) | /* M */
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((len_len - 1) << AES_AES_CTRL_CCM_L_S) | /* L */
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AES_AES_CTRL_CCM | /* CCM */
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AES_AES_CTRL_CTR_WIDTH_128 | /* CTR width 128 */
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AES_AES_CTRL_CTR | /* CTR */
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(encrypt ? AES_AES_CTRL_DIRECTION_ENCRYPT : 0); /* En/decryption */
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/* Workaround for AES registers not retained after PM2 */
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REG(AES_CTRL_INT_CFG) = AES_CTRL_INT_CFG_LEVEL;
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_DMA_IN_DONE |
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AES_CTRL_INT_EN_RESULT_AV;
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REG(AES_CTRL_ALG_SEL) = AES_CTRL_ALG_SEL_AES;
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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REG(AES_KEY_STORE_READ_AREA) = key_area;
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/* Wait until key is loaded to the AES module */
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while(REG(AES_KEY_STORE_READ_AREA) & AES_KEY_STORE_READ_AREA_BUSY);
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/* Check for Key Store read error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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/* Clear the Keystore Read error bit */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return AES_KEYSTORE_READ_ERROR;
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}
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/* Prepare the encryption initialization vector
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/* Prepare the crypto initialization vector
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* Flags: L' = L - 1 */
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((uint8_t *)iv)[0] = len_len - 1;
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/* Nonce */
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@ -93,134 +74,31 @@ ccm_auth_encrypt_start(uint8_t len_len, uint8_t key_area, const void *nonce,
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/* Initialize counter to 0 */
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rom_util_memset(&((uint8_t *)iv)[16 - len_len], 0, len_len);
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/* Write initialization vector */
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REG(AES_AES_IV_0) = iv[0];
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REG(AES_AES_IV_1) = iv[1];
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REG(AES_AES_IV_2) = iv[2];
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REG(AES_AES_IV_3) = iv[3];
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return aes_auth_crypt_start(ctrl, key_area, iv, adata, adata_len,
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data, data, data_len, process);
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t
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ccm_auth_crypt_get_result(const void *cdata, uint16_t cdata_len,
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void *mic, uint8_t mic_len)
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{
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uint32_t tag[4];
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uint16_t data_len;
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uint8_t ret;
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/* Program AES-CCM encryption */
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REG(AES_AES_CTRL) = AES_AES_CTRL_SAVE_CONTEXT | /* Save context */
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(((MAX(mic_len, 2) - 2) >> 1) << AES_AES_CTRL_CCM_M_S) | /* M */
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((len_len - 1) << AES_AES_CTRL_CCM_L_S) | /* L */
|
||||
AES_AES_CTRL_CCM | /* CCM */
|
||||
AES_AES_CTRL_CTR_WIDTH_128 | /* CTR width 128 */
|
||||
AES_AES_CTRL_CTR | /* CTR */
|
||||
AES_AES_CTRL_DIRECTION_ENCRYPT; /* Encryption */
|
||||
ret = aes_auth_crypt_get_result(NULL, tag);
|
||||
if(ret != CRYPTO_SUCCESS) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Write the length of the crypto block (lo) */
|
||||
REG(AES_AES_C_LENGTH_0) = pdata_len;
|
||||
/* Write the length of the crypto block (hi) */
|
||||
REG(AES_AES_C_LENGTH_1) = 0;
|
||||
|
||||
/* Write the length of the AAD data block (may be non-block size-aligned) */
|
||||
REG(AES_AES_AUTH_LENGTH) = adata_len;
|
||||
|
||||
if(adata_len != 0) {
|
||||
/* Configure DMAC to fetch the AAD data
|
||||
* Enable DMA channel 0 */
|
||||
REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
|
||||
/* Base address of the AAD input data in ext. memory */
|
||||
REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)adata;
|
||||
/* AAD data length in bytes */
|
||||
REG(AES_DMAC_CH0_DMALENGTH) = adata_len;
|
||||
|
||||
/* Wait for completion of the AAD data transfer, DMA_IN_DONE */
|
||||
while(!(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_IN_DONE));
|
||||
|
||||
/* Check for the absence of error */
|
||||
if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
|
||||
/* Clear the DMA error */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR;
|
||||
/* Disable the master control / DMA clock */
|
||||
REG(AES_CTRL_ALG_SEL) = 0x00000000;
|
||||
return CRYPTO_DMA_BUS_ERROR;
|
||||
if(cdata != NULL) {
|
||||
/* Check MIC */
|
||||
data_len = cdata_len - mic_len;
|
||||
if(rom_util_memcmp(tag, &((const uint8_t *)cdata)[data_len], mic_len)) {
|
||||
return AES_AUTHENTICATION_FAILED;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear interrupt status */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
|
||||
AES_CTRL_INT_CLR_RESULT_AV;
|
||||
|
||||
if(process != NULL) {
|
||||
crypto_register_process_notification(process);
|
||||
nvic_interrupt_unpend(NVIC_INT_AES);
|
||||
nvic_interrupt_enable(NVIC_INT_AES);
|
||||
}
|
||||
|
||||
/* Enable result available bit in interrupt enable */
|
||||
REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_RESULT_AV;
|
||||
|
||||
if(pdata_len != 0) {
|
||||
/* Configure DMAC
|
||||
* Enable DMA channel 0 */
|
||||
REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
|
||||
/* Base address of the payload data in ext. memory */
|
||||
REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)pdata;
|
||||
/* Payload data length in bytes */
|
||||
REG(AES_DMAC_CH0_DMALENGTH) = pdata_len;
|
||||
|
||||
/* Enable DMA channel 1 */
|
||||
REG(AES_DMAC_CH1_CTRL) = AES_DMAC_CH_CTRL_EN;
|
||||
/* Base address of the output data buffer */
|
||||
REG(AES_DMAC_CH1_EXTADDR) = (uint32_t)pdata;
|
||||
/* Output data length in bytes */
|
||||
REG(AES_DMAC_CH1_DMALENGTH) = pdata_len;
|
||||
}
|
||||
|
||||
return CRYPTO_SUCCESS;
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
uint8_t
|
||||
ccm_auth_encrypt_check_status(void)
|
||||
{
|
||||
return !!(REG(AES_CTRL_INT_STAT) &
|
||||
(AES_CTRL_INT_STAT_DMA_BUS_ERR | AES_CTRL_INT_STAT_KEY_ST_WR_ERR |
|
||||
AES_CTRL_INT_STAT_KEY_ST_RD_ERR | AES_CTRL_INT_STAT_RESULT_AV));
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
uint8_t
|
||||
ccm_auth_encrypt_get_result(void *mic, uint8_t mic_len)
|
||||
{
|
||||
uint32_t aes_ctrl_int_stat;
|
||||
uint32_t tag[4];
|
||||
|
||||
aes_ctrl_int_stat = REG(AES_CTRL_INT_STAT);
|
||||
/* Clear the error bits */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR |
|
||||
AES_CTRL_INT_CLR_KEY_ST_WR_ERR |
|
||||
AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
|
||||
|
||||
nvic_interrupt_disable(NVIC_INT_AES);
|
||||
crypto_register_process_notification(NULL);
|
||||
|
||||
/* Disable the master control / DMA clock */
|
||||
REG(AES_CTRL_ALG_SEL) = 0x00000000;
|
||||
|
||||
if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
|
||||
return CRYPTO_DMA_BUS_ERROR;
|
||||
}
|
||||
if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_WR_ERR) {
|
||||
return AES_KEYSTORE_WRITE_ERROR;
|
||||
}
|
||||
if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
|
||||
return AES_KEYSTORE_READ_ERROR;
|
||||
}
|
||||
|
||||
/* Read tag
|
||||
* Wait for the context ready bit */
|
||||
while(!(REG(AES_AES_CTRL) & AES_AES_CTRL_SAVED_CONTEXT_READY));
|
||||
|
||||
/* Read the tag registers */
|
||||
tag[0] = REG(AES_AES_TAG_OUT_0);
|
||||
tag[1] = REG(AES_AES_TAG_OUT_1);
|
||||
tag[2] = REG(AES_AES_TAG_OUT_2);
|
||||
tag[3] = REG(AES_AES_TAG_OUT_3);
|
||||
|
||||
/* Clear the interrupt status */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
|
||||
AES_CTRL_INT_CLR_RESULT_AV;
|
||||
|
||||
/* Copy tag to MIC */
|
||||
rom_util_memcpy(mic, tag, mic_len);
|
||||
|
||||
|
|
@ -228,186 +106,36 @@ ccm_auth_encrypt_get_result(void *mic, uint8_t mic_len)
|
|||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
uint8_t
|
||||
ccm_auth_encrypt_start(uint8_t len_len, uint8_t key_area, const void *nonce,
|
||||
const void *adata, uint16_t adata_len, void *pdata,
|
||||
uint16_t pdata_len, uint8_t mic_len,
|
||||
struct process *process)
|
||||
{
|
||||
return ccm_auth_crypt_start(true, len_len, key_area, nonce, adata, adata_len,
|
||||
pdata, pdata_len, mic_len, process);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
uint8_t
|
||||
ccm_auth_encrypt_get_result(void *mic, uint8_t mic_len)
|
||||
{
|
||||
return ccm_auth_crypt_get_result(NULL, 0, mic, mic_len);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
uint8_t
|
||||
ccm_auth_decrypt_start(uint8_t len_len, uint8_t key_area, const void *nonce,
|
||||
const void *adata, uint16_t adata_len, void *cdata,
|
||||
uint16_t cdata_len, uint8_t mic_len,
|
||||
struct process *process)
|
||||
{
|
||||
uint16_t pdata_len = cdata_len - mic_len;
|
||||
uint32_t iv[4];
|
||||
uint16_t data_len = cdata_len - mic_len;
|
||||
|
||||
if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
|
||||
return CRYPTO_RESOURCE_IN_USE;
|
||||
}
|
||||
|
||||
/* Workaround for AES registers not retained after PM2 */
|
||||
REG(AES_CTRL_INT_CFG) = AES_CTRL_INT_CFG_LEVEL;
|
||||
REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_DMA_IN_DONE |
|
||||
AES_CTRL_INT_EN_RESULT_AV;
|
||||
|
||||
REG(AES_CTRL_ALG_SEL) = AES_CTRL_ALG_SEL_AES;
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
|
||||
AES_CTRL_INT_CLR_RESULT_AV;
|
||||
|
||||
REG(AES_KEY_STORE_READ_AREA) = key_area;
|
||||
|
||||
/* Wait until key is loaded to the AES module */
|
||||
while(REG(AES_KEY_STORE_READ_AREA) & AES_KEY_STORE_READ_AREA_BUSY);
|
||||
|
||||
/* Check for Key Store read error */
|
||||
if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
|
||||
/* Clear the Keystore Read error bit */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
|
||||
/* Disable the master control / DMA clock */
|
||||
REG(AES_CTRL_ALG_SEL) = 0x00000000;
|
||||
return AES_KEYSTORE_READ_ERROR;
|
||||
}
|
||||
|
||||
/* Prepare the decryption initialization vector
|
||||
* Flags: L' = L - 1 */
|
||||
((uint8_t *)iv)[0] = len_len - 1;
|
||||
/* Nonce */
|
||||
rom_util_memcpy(&((uint8_t *)iv)[1], nonce, 15 - len_len);
|
||||
/* Initialize counter to 0 */
|
||||
rom_util_memset(&((uint8_t *)iv)[16 - len_len], 0, len_len);
|
||||
|
||||
/* Write initialization vector */
|
||||
REG(AES_AES_IV_0) = iv[0];
|
||||
REG(AES_AES_IV_1) = iv[1];
|
||||
REG(AES_AES_IV_2) = iv[2];
|
||||
REG(AES_AES_IV_3) = iv[3];
|
||||
|
||||
/* Program AES-CCM decryption */
|
||||
REG(AES_AES_CTRL) = AES_AES_CTRL_SAVE_CONTEXT | /* Save context */
|
||||
(((MAX(mic_len, 2) - 2) >> 1) << AES_AES_CTRL_CCM_M_S) | /* M */
|
||||
((len_len - 1) << AES_AES_CTRL_CCM_L_S) | /* L */
|
||||
AES_AES_CTRL_CCM | /* CCM */
|
||||
AES_AES_CTRL_CTR_WIDTH_128 | /* CTR width 128 */
|
||||
AES_AES_CTRL_CTR; /* CTR */
|
||||
|
||||
/* Write the length of the crypto block (lo) */
|
||||
REG(AES_AES_C_LENGTH_0) = pdata_len;
|
||||
/* Write the length of the crypto block (hi) */
|
||||
REG(AES_AES_C_LENGTH_1) = 0;
|
||||
|
||||
/* Write the length of the AAD data block (may be non-block size-aligned) */
|
||||
REG(AES_AES_AUTH_LENGTH) = adata_len;
|
||||
|
||||
if(adata_len != 0) {
|
||||
/* Configure DMAC to fetch the AAD data
|
||||
* Enable DMA channel 0 */
|
||||
REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
|
||||
/* Base address of the AAD input data in ext. memory */
|
||||
REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)adata;
|
||||
/* AAD data length in bytes */
|
||||
REG(AES_DMAC_CH0_DMALENGTH) = adata_len;
|
||||
|
||||
/* Wait for completion of the AAD data transfer, DMA_IN_DONE */
|
||||
while(!(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_IN_DONE));
|
||||
|
||||
/* Check for the absence of error */
|
||||
if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
|
||||
/* Clear the DMA error */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR;
|
||||
/* Disable the master control / DMA clock */
|
||||
REG(AES_CTRL_ALG_SEL) = 0x00000000;
|
||||
return CRYPTO_DMA_BUS_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear interrupt status */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
|
||||
AES_CTRL_INT_CLR_RESULT_AV;
|
||||
|
||||
if(process != NULL) {
|
||||
crypto_register_process_notification(process);
|
||||
nvic_interrupt_unpend(NVIC_INT_AES);
|
||||
nvic_interrupt_enable(NVIC_INT_AES);
|
||||
}
|
||||
|
||||
/* Enable result available bit in interrupt enable */
|
||||
REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_RESULT_AV;
|
||||
|
||||
if(pdata_len != 0) {
|
||||
/* Configure DMAC
|
||||
* Enable DMA channel 0 */
|
||||
REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
|
||||
/* Base address of the payload data in ext. memory */
|
||||
REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)cdata;
|
||||
/* Payload data length in bytes */
|
||||
REG(AES_DMAC_CH0_DMALENGTH) = pdata_len;
|
||||
|
||||
/* Enable DMA channel 1 */
|
||||
REG(AES_DMAC_CH1_CTRL) = AES_DMAC_CH_CTRL_EN;
|
||||
/* Base address of the output data buffer */
|
||||
REG(AES_DMAC_CH1_EXTADDR) = (uint32_t)cdata;
|
||||
/* Output data length in bytes */
|
||||
REG(AES_DMAC_CH1_DMALENGTH) = pdata_len;
|
||||
}
|
||||
|
||||
return CRYPTO_SUCCESS;
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
uint8_t
|
||||
ccm_auth_decrypt_check_status(void)
|
||||
{
|
||||
/* Check if result is available or some error has occured */
|
||||
return ccm_auth_encrypt_check_status();
|
||||
return ccm_auth_crypt_start(false, len_len, key_area, nonce, adata, adata_len,
|
||||
cdata, data_len, mic_len, process);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
uint8_t
|
||||
ccm_auth_decrypt_get_result(const void *cdata, uint16_t cdata_len,
|
||||
void *mic, uint8_t mic_len)
|
||||
{
|
||||
uint32_t aes_ctrl_int_stat;
|
||||
uint16_t pdata_len = cdata_len - mic_len;
|
||||
uint32_t tag[4];
|
||||
|
||||
aes_ctrl_int_stat = REG(AES_CTRL_INT_STAT);
|
||||
/* Clear the error bits */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR |
|
||||
AES_CTRL_INT_CLR_KEY_ST_WR_ERR |
|
||||
AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
|
||||
|
||||
nvic_interrupt_disable(NVIC_INT_AES);
|
||||
crypto_register_process_notification(NULL);
|
||||
|
||||
/* Disable the master control / DMA clock */
|
||||
REG(AES_CTRL_ALG_SEL) = 0x00000000;
|
||||
|
||||
if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
|
||||
return CRYPTO_DMA_BUS_ERROR;
|
||||
}
|
||||
if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_WR_ERR) {
|
||||
return AES_KEYSTORE_WRITE_ERROR;
|
||||
}
|
||||
if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
|
||||
return AES_KEYSTORE_READ_ERROR;
|
||||
}
|
||||
|
||||
/* Read tag
|
||||
* Wait for the context ready bit */
|
||||
while(!(REG(AES_AES_CTRL) & AES_AES_CTRL_SAVED_CONTEXT_READY));
|
||||
|
||||
/* Read the tag registers */
|
||||
tag[0] = REG(AES_AES_TAG_OUT_0);
|
||||
tag[1] = REG(AES_AES_TAG_OUT_1);
|
||||
tag[2] = REG(AES_AES_TAG_OUT_2);
|
||||
tag[3] = REG(AES_AES_TAG_OUT_3);
|
||||
|
||||
/* Clear the interrupt status */
|
||||
REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
|
||||
AES_CTRL_INT_CLR_RESULT_AV;
|
||||
|
||||
/* Check MIC */
|
||||
if(rom_util_memcmp(tag, &((const uint8_t *)cdata)[pdata_len], mic_len)) {
|
||||
return CCM_AUTHENTICATION_FAILED;
|
||||
}
|
||||
|
||||
/* Copy tag to MIC */
|
||||
rom_util_memcpy(mic, tag, mic_len);
|
||||
|
||||
return CRYPTO_SUCCESS;
|
||||
}
|
||||
__attribute__ ((alias("ccm_auth_crypt_get_result")));
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -54,12 +54,6 @@
|
|||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** \name AES-CCM driver return codes
|
||||
* @{
|
||||
*/
|
||||
#define CCM_AUTHENTICATION_FAILED 7
|
||||
/** @} */
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** \name AES-CCM functions
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -86,7 +80,7 @@ uint8_t ccm_auth_encrypt_start(uint8_t len_len, uint8_t key_area,
|
|||
* \retval false Result not yet available, and no error occurred
|
||||
* \retval true Result available, or error occurred
|
||||
*/
|
||||
uint8_t ccm_auth_encrypt_check_status(void);
|
||||
#define ccm_auth_encrypt_check_status aes_auth_crypt_check_status
|
||||
|
||||
/** \brief Gets the result of the CCM authentication and encryption operation
|
||||
* \param mic Pointer to authentication field, or \c NULL
|
||||
|
|
@ -118,7 +112,7 @@ uint8_t ccm_auth_decrypt_start(uint8_t len_len, uint8_t key_area,
|
|||
* \retval false Result not yet available, and no error occurred
|
||||
* \retval true Result available, or error occurred
|
||||
*/
|
||||
uint8_t ccm_auth_decrypt_check_status(void);
|
||||
#define ccm_auth_decrypt_check_status aes_auth_crypt_check_status
|
||||
|
||||
/** \brief Gets the result of the CCM authentication checking and decryption operation
|
||||
* \param cdata Pointer to encrypted and authenticated message
|
||||
|
|
|
|||
Loading…
Reference in a new issue