Add initial ADuCRF101 CPU support
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Jim Paris
parent
2be02cd269
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baa6058839
12 changed files with 1003 additions and 0 deletions
105
cpu/arm/aducrf101/Common/GCC/ADuCRF101.ld
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105
cpu/arm/aducrf101/Common/GCC/ADuCRF101.ld
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/**
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* Copyright (c) 2014, Analog Devices, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted (subject to the limitations in the
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* disclaimer below) provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* - Neither the name of Analog Devices, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(Reset_Handler)
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MEMORY
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{
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flash (rx) : org = 0x00000000, len = 128k
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ram (rwx) : org = 0x20000000, len = 16k
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}
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SECTIONS
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{
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.vectors : {
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__vectors_start = .;
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KEEP(*(.vectors))
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. = ALIGN(4);
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} >flash
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.text : {
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. = ALIGN(4);
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*(.text)
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*(.text.*)
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etext = .;
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} >flash
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.ARM.ex : {
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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__exidx_start = .;
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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__exidx_end = .;
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} >flash
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.rodata : {
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. = ALIGN(4);
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*(.rodata)
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*(.rodata.*)
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. = ALIGN(4);
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__rodata_end = .;
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} >flash
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.data : {
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/* Initialized data is placed in flash, and will get
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copied to RAM by crt0.S */
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. = ALIGN(4);
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__data_flash_start = LOADADDR(.data);
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__data_start = .;
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*(.data)
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*(.data.*)
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/* Code that goes into RAM also ends up here, and
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gets copied along with the data section. */
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*(.ramtext*)
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__data_end = .;
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edata = .;
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} > ram AT > flash
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.bss : {
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/* Stack is in BSS */
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. = ALIGN(8);
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__bss_start = .;
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*(.bss.stack)
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end = .;
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end = .;
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} > ram
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}
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184
cpu/arm/aducrf101/Common/GCC/crt0.S
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184
cpu/arm/aducrf101/Common/GCC/crt0.S
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@ -0,0 +1,184 @@
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/**
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* Copyright (c) 2014, Analog Devices, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted (subject to the limitations in the
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* disclaimer below) provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* - Neither the name of Analog Devices, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __STACK_SIZE
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#define __STACK_SIZE 1024
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#endif
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.equ SCB_VTOR, 0xE000ED08
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/* Stack */
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.section .bss.stack
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stack_start:
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.space __STACK_SIZE, 0
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stack_end:
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.global stack_end
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/* Vector table */
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.macro handler name
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.long \name\()
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.weak \name\()
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.set \name\(), unhandled_vector
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.endm
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.macro handler_reserved
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.long 0
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.endm
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.section .vectors, "a", %progbits
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vectors:
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.long stack_end
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.long Reset_Handler
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/* Cortex-M3 core interrupts */
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handler NMI_Handler
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handler HardFault_Handler
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handler MemManage_Handler
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handler BusFault_Handler
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handler UsageFault_Handler
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handler_reserved
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handler_reserved
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handler_reserved
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handler_reserved
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handler SVC_Handler
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handler DebugMon_Handler
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handler_reserved
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handler PendSV_Handler
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handler SysTick_Handler
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/* ADuCRF101 external interrupts */
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handler WakeUp_Int_Handler
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handler Ext_Int0_Handler
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handler Ext_Int1_Handler
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handler Ext_Int2_Handler
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handler Ext_Int3_Handler
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handler Ext_Int4_Handler
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handler Ext_Int5_Handler
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handler Ext_Int6_Handler
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handler Ext_Int7_Handler
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handler Ext_Int8_Handler
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handler WDog_Tmr_Int_Handler
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handler_reserved
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handler GP_Tmr0_Int_Handler
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handler GP_Tmr1_Int_Handler
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handler ADC0_Int_Handler
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handler Flsh_Int_Handler
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handler UART_Int_Handler
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handler SPI0_Int_Handler
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handler SPI1_Int_Handler
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handler I2C0_Slave_Int_Handler
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handler I2C0_Master_Int_Handler
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handler_reserved
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handler_reserved
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handler DMA_Err_Int_Handler
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handler DMA_SPI1_TX_Int_Handler
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handler DMA_SPI1_RX_Int_Handler
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handler DMA_UART_TX_Int_Handler
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handler DMA_UART_RX_Int_Handler
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handler DMA_I2C0_STX_Int_Handler
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handler DMA_I2C0_SRX_Int_Handler
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handler DMA_I2C0_MTX_Int_Handler
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handler DMA_I2C0_MRX_Int_Handler
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handler_reserved
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handler_reserved
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handler_reserved
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handler DMA_ADC_Int_Handler
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handler DMA_SPI0_TX_Int_Handler
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handler DMA_SPI0_RX_Int_Handler
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handler PWMTrip_Int_Handler
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handler PWM0_Int_Handler
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handler PWM1_Int_Handler
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handler PWM2_Int_Handler
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handler PWM3_Int_Handler
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/* Reset handler */
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.section .text
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.syntax unified
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.code 16
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.global Reset_Handler
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.thumb_func
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Reset_Handler:
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/* Set up some basics, in case we came here from a call
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rather than system reset. */
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/* Disable interrupts */
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cpsid i
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/* Privileged mode, main stack, no floating point */
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mov r0, #0
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msr control, r0
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isb
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/* Point vector table to the right place */
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ldr r0, =__vectors_start
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ldr r1, =SCB_VTOR
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str r0, [r1]
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/* Load initial stack pointer */
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ldr r0, =stack_end
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mov sp, r0
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isb
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/* Clear BSS */
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mov r0, #0
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ldr r1, =__bss_start
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ldr r2, =__bss_end
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zero_bss_loop:
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cmp r1, r2
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it lt
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strlt r0, [r1], #4
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blt zero_bss_loop
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/* Copy initialized data from flash to RAM */
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ldr r0, =__data_flash_start
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ldr r1, =__data_start
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ldr r2, =__data_end
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copy_data_loop:
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ldr r3, [r0], #4
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cmp r1, r2
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it lt
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strlt r3, [r1], #4
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blt copy_data_loop
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/* We can run C code now */
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bl main
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/* If main returned, just loop */
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b .
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/* Handler for otherwise unhandled vectors */
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.section .text,"ax",%progbits
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.thumb_func
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unhandled_vector:
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b unhandled_vector
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