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enc28j60: Add workaround for erratum #2 "CLKRDY set early"

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A delay of 1 ms must be added after the System Reset Command. Still wait
for ESTAT.CLKRDY afterwards as a precaution.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This commit is contained in:
Benoît Thébaudeau 2015-07-14 18:46:56 +02:00
parent 48f269e4f5
commit ba6a0bc381
1 changed files with 5 additions and 2 deletions
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7
dev/enc28j60/enc28j60.c
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@ -298,11 +298,14 @@ reset(void)
see Section 2.2 “Oscillator Start-up Timer. see Section 2.2 “Oscillator Start-up Timer.
*/ */
softreset();
/* Workaround for erratum #2. */
clock_delay_usec(1000);
/* Wait for OST */ /* Wait for OST */
while((readreg(ESTAT) & ESTAT_CLKRDY) == 0); while((readreg(ESTAT) & ESTAT_CLKRDY) == 0);
softreset();
setregbank(ERXTX_BANK); setregbank(ERXTX_BANK);
/* Set up receive buffer */ /* Set up receive buffer */
writereg(ERXSTL, RX_BUF_START & 0xff); writereg(ERXSTL, RX_BUF_START & 0xff);