Merge pull request #1042 from uknoblic/cc2538_spi
CC2538: added support for SSI1
This commit is contained in:
Benoît Thébaudeau
commit
b8ff3251e1
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@ -86,7 +86,7 @@ void spi_init(void);
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#define SPI_FLUSH() \
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do { \
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SPI_RXBUF; \
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} while(0);
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} while(0)
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#endif
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#endif /* SPI_H_ */
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@ -129,12 +129,18 @@
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#define CC_CONCAT2(s1, s2) s1##s2
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/**
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* A C preprocessing macro for concatenating to
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* strings.
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* A C preprocessing macro for concatenating two preprocessor tokens.
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*
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* We need use two macros (CC_CONCAT and CC_CONCAT2) in order to allow
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* concatenation of two \#defined macros.
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*/
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#define CC_CONCAT(s1, s2) CC_CONCAT2(s1, s2)
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#define CC_CONCAT_EXT_2(s1, s2) CC_CONCAT2(s1, s2)
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/**
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* A C preprocessing macro for concatenating three preprocessor tokens.
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*/
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#define CC_CONCAT3(s1, s2, s3) s1##s2##s3
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#define CC_CONCAT_EXT_3(s1, s2, s3) CC_CONCAT3(s1, s2, s3)
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#endif /* CC_H_ */
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@ -1,5 +1,9 @@
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/*
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* Copyright (c) 2013, University of Michigan.
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*
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* Copyright (c) 2015, Weptech elektronik GmbH
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* Author: Ulf Knoblich, ulf.knoblich@weptech.de
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -41,102 +45,281 @@
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#include "dev/spi.h"
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#include "dev/ssi.h"
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#include "dev/gpio.h"
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/*---------------------------------------------------------------------------*/
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/* Check port / pin settings for SPI0 and provide default values for spi_cfg */
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#ifndef SPI0_CLK_PORT
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#define SPI0_CLK_PORT (-1)
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#endif
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#ifndef SPI0_CLK_PIN
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#define SPI0_CLK_PIN (-1)
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#endif
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#if SPI0_CLK_PORT >= 0 && SPI0_CLK_PIN < 0 || \
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SPI0_CLK_PORT < 0 && SPI0_CLK_PIN >= 0
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#error Both SPI0_CLK_PORT and SPI0_CLK_PIN must be valid or invalid
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#endif
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#define SPI_CLK_PORT_BASE GPIO_PORT_TO_BASE(SPI_CLK_PORT)
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#define SPI_CLK_PIN_MASK GPIO_PIN_MASK(SPI_CLK_PIN)
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#define SPI_MOSI_PORT_BASE GPIO_PORT_TO_BASE(SPI_MOSI_PORT)
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#define SPI_MOSI_PIN_MASK GPIO_PIN_MASK(SPI_MOSI_PIN)
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#define SPI_MISO_PORT_BASE GPIO_PORT_TO_BASE(SPI_MISO_PORT)
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#define SPI_MISO_PIN_MASK GPIO_PIN_MASK(SPI_MISO_PIN)
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#ifndef SPI0_TX_PORT
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#define SPI0_TX_PORT (-1)
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#endif
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#ifndef SPI0_TX_PIN
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#define SPI0_TX_PIN (-1)
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#endif
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#if SPI0_TX_PORT >= 0 && SPI0_TX_PIN < 0 || \
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SPI0_TX_PORT < 0 && SPI0_TX_PIN >= 0
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#error Both SPI0_TX_PORT and SPI0_TX_PIN must be valid or invalid
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#endif
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/**
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* \brief Initialize the SPI bus.
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*
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* This SPI init() function uses the following defines to set the pins:
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* SPI_CLK_PORT SPI_CLK_PIN
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* SPI_MOSI_PORT SPI_MOSI_PIN
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* SPI_MISO_PORT SPI_MISO_PIN
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*
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* This sets the mode to Motorola SPI with the following format options:
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* Clock phase: 1; data captured on second (rising) edge
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* Clock polarity: 1; clock is high when idle
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* Data size: 8 bits
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*/
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#ifndef SPI0_RX_PORT
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#define SPI0_RX_PORT (-1)
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#endif
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#ifndef SPI0_RX_PIN
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#define SPI0_RX_PIN (-1)
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#endif
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#if SPI0_RX_PORT >= 0 && SPI0_RX_PIN < 0 || \
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SPI0_RX_PORT < 0 && SPI0_RX_PIN >= 0
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#error Both SPI0_RX_PORT and SPI0_RX_PIN must be valid or invalid
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#endif
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/* Here we check that either all or none of the ports are defined. As
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we did already check that both ports + pins are either defined or
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not for every pin, this means that we can check for an incomplete
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configuration by only looking at the port defines */
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/* If some SPI0 pads are valid */
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#if SPI0_CLK_PORT >= 0 || SPI0_TX_PORT >= 0 || SPI0_RX_PORT >= 0
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/* but not all */
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#if SPI0_CLK_PORT < 0 || SPI0_TX_PORT < 0 || SPI0_RX_PORT < 0
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#error Some SPI0 pad definitions are invalid
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#endif
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#define SPI0_PADS_VALID
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#endif
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/*---------------------------------------------------------------------------*/
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/* Check port / pin settings for SPI1 and provide default values for spi_cfg */
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#ifndef SPI1_CLK_PORT
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#define SPI1_CLK_PORT (-1)
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#endif
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#ifndef SPI1_CLK_PIN
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#define SPI1_CLK_PIN (-1)
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#endif
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#if SPI1_CLK_PORT >= 0 && SPI1_CLK_PIN < 0 || \
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SPI1_CLK_PORT < 0 && SPI1_CLK_PIN >= 0
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#error Both SPI1_CLK_PORT and SPI1_CLK_PIN must be valid or invalid
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#endif
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#ifndef SPI1_TX_PORT
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#define SPI1_TX_PORT (-1)
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#endif
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#ifndef SPI1_TX_PIN
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#define SPI1_TX_PIN (-1)
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#endif
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#if SPI1_TX_PORT >= 0 && SPI1_TX_PIN < 0 || \
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SPI1_TX_PORT < 0 && SPI1_TX_PIN >= 0
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#error Both SPI1_TX_PORT and SPI1_TX_PIN must be valid or invalid
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#endif
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#ifndef SPI1_RX_PORT
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#define SPI1_RX_PORT (-1)
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#endif
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#ifndef SPI1_RX_PIN
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#define SPI1_RX_PIN (-1)
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#endif
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#if SPI1_RX_PORT >= 0 && SPI1_RX_PIN < 0 || \
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SPI1_RX_PORT < 0 && SPI1_RX_PIN >= 0
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#error Both SPI1_RX_PORT and SPI1_RX_PIN must be valid or invalid
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#endif
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/* If some SPI1 pads are valid */
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#if SPI1_CLK_PORT >= 0 || SPI1_TX_PORT >= 0 || SPI1_RX_PORT >= 0
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/* but not all */
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#if SPI1_CLK_PORT < 0 || SPI1_TX_PORT < 0 || SPI1_RX_PORT < 0
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#error Some SPI1 pad definitions are invalid
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#endif
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#define SPI1_PADS_VALID
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#endif
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#ifdef SPI_DEFAULT_INSTANCE
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#if SPI_DEFAULT_INSTANCE == 0
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#ifndef SPI0_PADS_VALID
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#error SPI_DEFAULT_INSTANCE is set to SPI0, but its pads are not valid
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#endif
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#elif SPI_DEFAULT_INSTANCE == 1
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#ifndef SPI1_PADS_VALID
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#error SPI_DEFAULT_INSTANCE is set to SPI1, but its pads are not valid
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#endif
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#endif
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#endif
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#if (SPI0_CPRS_CPSDVSR & 1) == 1 || SPI0_CPRS_CPSDVSR < 2 || SPI0_CPRS_CPSDVSR > 254
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#error SPI0_CPRS_CPSDVSR must be an even number between 2 and 254
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#endif
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#if (SPI1_CPRS_CPSDVSR & 1) == 1 || SPI1_CPRS_CPSDVSR < 2 || SPI1_CPRS_CPSDVSR > 254
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#error SPI1_CPRS_CPSDVSR must be an even number between 2 and 254
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#endif
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/*---------------------------------------------------------------------------*/
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typedef struct {
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int8_t port;
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int8_t pin;
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} spi_pad_t;
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typedef struct {
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uint32_t base;
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uint32_t ioc_ssirxd_ssi;
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uint32_t ioc_pxx_sel_ssi_clkout;
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uint32_t ioc_pxx_sel_ssi_txd;
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uint8_t ssi_cprs_cpsdvsr;
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spi_pad_t clk;
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spi_pad_t tx;
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spi_pad_t rx;
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} spi_regs_t;
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/*---------------------------------------------------------------------------*/
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static const spi_regs_t spi_regs[SSI_INSTANCE_COUNT] = {
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{
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.base = SSI0_BASE,
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.ioc_ssirxd_ssi = IOC_SSIRXD_SSI0,
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.ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI0_CLKOUT,
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.ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI0_TXD,
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.ssi_cprs_cpsdvsr = SPI0_CPRS_CPSDVSR,
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.clk = { SPI0_CLK_PORT, SPI0_CLK_PIN },
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.tx = { SPI0_TX_PORT, SPI0_TX_PIN },
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.rx = { SPI0_RX_PORT, SPI0_RX_PIN }
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}, {
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.base = SSI1_BASE,
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.ioc_ssirxd_ssi = IOC_SSIRXD_SSI1,
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.ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI1_CLKOUT,
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.ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI1_TXD,
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.ssi_cprs_cpsdvsr = SPI1_CPRS_CPSDVSR,
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.clk = { SPI1_CLK_PORT, SPI1_CLK_PIN },
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.tx = { SPI1_TX_PORT, SPI1_TX_PIN },
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.rx = { SPI1_RX_PORT, SPI1_RX_PIN }
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}
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};
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/*---------------------------------------------------------------------------*/
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/* Deprecated function call provided for compatibility reasons */
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#ifdef SPI_DEFAULT_INSTANCE
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void
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spi_init(void)
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{
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spi_enable();
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spix_init(SPI_DEFAULT_INSTANCE);
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}
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#endif /* #ifdef SPI_DEFAULT_INSTANCE */
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/*---------------------------------------------------------------------------*/
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void
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spix_init(uint8_t spi)
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{
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const spi_regs_t *regs;
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if(spi >= SSI_INSTANCE_COUNT) {
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return;
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}
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regs = &spi_regs[spi];
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if(regs->clk.port < 0) {
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/* Port / pin configuration invalid. We checked for completeness
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above. If clk.port is < 0, this means that all other defines are
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< 0 as well */
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return;
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}
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spix_enable(spi);
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/* Start by disabling the peripheral before configuring it */
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REG(SSI0_BASE + SSI_CR1) = 0;
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REG(regs->base + SSI_CR1) = 0;
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/* Set the IO clock as the SSI clock */
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REG(SSI0_BASE + SSI_CC) = 1;
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REG(regs->base + SSI_CC) = 1;
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/* Set the mux correctly to connect the SSI pins to the correct GPIO pins */
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ioc_set_sel(SPI_CLK_PORT, SPI_CLK_PIN, IOC_PXX_SEL_SSI0_CLKOUT);
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ioc_set_sel(SPI_MOSI_PORT, SPI_MOSI_PIN, IOC_PXX_SEL_SSI0_TXD);
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REG(IOC_SSIRXD_SSI0) = (SPI_MISO_PORT * 8) + SPI_MISO_PIN;
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ioc_set_sel(regs->clk.port,
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regs->clk.pin,
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regs->ioc_pxx_sel_ssi_clkout);
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ioc_set_sel(regs->tx.port,
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regs->tx.pin,
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regs->ioc_pxx_sel_ssi_txd);
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REG(regs->ioc_ssirxd_ssi) = (regs->rx.port * 8) + regs->rx.pin;
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/* Put all the SSI gpios into peripheral mode */
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GPIO_PERIPHERAL_CONTROL(SPI_CLK_PORT_BASE, SPI_CLK_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(SPI_MOSI_PORT_BASE, SPI_MOSI_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(SPI_MISO_PORT_BASE, SPI_MISO_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->clk.port),
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GPIO_PIN_MASK(regs->clk.pin));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->tx.port),
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GPIO_PIN_MASK(regs->tx.pin));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
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GPIO_PIN_MASK(regs->rx.pin));
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/* Disable any pull ups or the like */
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ioc_set_over(SPI_CLK_PORT, SPI_CLK_PIN, IOC_OVERRIDE_DIS);
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ioc_set_over(SPI_MOSI_PORT, SPI_MOSI_PIN, IOC_OVERRIDE_DIS);
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ioc_set_over(SPI_MISO_PORT, SPI_MISO_PIN, IOC_OVERRIDE_DIS);
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ioc_set_over(regs->clk.port, regs->clk.pin, IOC_OVERRIDE_DIS);
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ioc_set_over(regs->tx.port, regs->tx.pin, IOC_OVERRIDE_DIS);
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ioc_set_over(regs->rx.port, regs->rx.pin, IOC_OVERRIDE_DIS);
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/* Configure the clock */
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REG(SSI0_BASE + SSI_CPSR) = 2;
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REG(regs->base + SSI_CPSR) = regs->ssi_cprs_cpsdvsr;
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/* Configure the default SPI options.
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/*
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* Configure the default SPI options.
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* mode: Motorola frame format
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* clock: High when idle
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* data: Valid on rising edges of the clock
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* bits: 8 byte data
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*/
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REG(SSI0_BASE + SSI_CR0) = SSI_CR0_SPH | SSI_CR0_SPO | (0x07);
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REG(regs->base + SSI_CR0) = SSI_CR0_SPH | SSI_CR0_SPO | (0x07);
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/* Enable the SSI */
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REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE;
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REG(regs->base + SSI_CR1) |= SSI_CR1_SSE;
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_cs_init(uint8_t port, uint8_t pin)
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spix_enable(uint8_t spi)
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{
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GPIO_SOFTWARE_CONTROL(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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if(spi >= SSI_INSTANCE_COUNT) {
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return;
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}
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REG(SYS_CTRL_RCGCSSI) |= (1 << spi);
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}
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/*---------------------------------------------------------------------------*/
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void
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spix_disable(uint8_t spi)
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{
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if(spi >= SSI_INSTANCE_COUNT) {
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return;
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}
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REG(SYS_CTRL_RCGCSSI) &= ~(1 << spi);
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}
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/*---------------------------------------------------------------------------*/
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void
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spix_set_mode(uint8_t spi,
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uint32_t frame_format,
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uint32_t clock_polarity,
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uint32_t clock_phase,
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uint32_t data_size)
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{
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const spi_regs_t *regs;
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if(spi >= SSI_INSTANCE_COUNT) {
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return;
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}
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regs = &spi_regs[spi];
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/* Disable the SSI peripheral to configure it */
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REG(regs->base + SSI_CR1) = 0;
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/* Configure the SSI options */
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REG(regs->base + SSI_CR0) = clock_phase |
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clock_polarity |
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frame_format |
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(data_size - 1);
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/* Re-enable the SSI */
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REG(regs->base + SSI_CR1) |= SSI_CR1_SSE;
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}
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/*---------------------------------------------------------------------------*/
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void
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spix_cs_init(uint8_t port, uint8_t pin)
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{
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GPIO_SOFTWARE_CONTROL(GPIO_PORT_TO_BASE(port),
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GPIO_PIN_MASK(pin));
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ioc_set_over(port, pin, IOC_OVERRIDE_DIS);
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GPIO_SET_OUTPUT(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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GPIO_SET_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_enable(void)
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{
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/* Enable the clock for the SSI peripheral */
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REG(SYS_CTRL_RCGCSSI) |= 1;
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_disable(void)
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{
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/* Gate the clock for the SSI peripheral */
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REG(SYS_CTRL_RCGCSSI) &= ~1;
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_set_mode(uint32_t frame_format, uint32_t clock_polarity,
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uint32_t clock_phase, uint32_t data_size)
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{
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/* Disable the SSI peripheral to configure it */
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REG(SSI0_BASE + SSI_CR1) = 0;
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/* Configure the SSI options */
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REG(SSI0_BASE + SSI_CR0) = clock_phase | clock_polarity | frame_format | (data_size - 1);
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/* Re-enable the SSI */
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REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE;
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}
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/** @} */
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@ -45,6 +45,12 @@
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#ifndef SSI_H_
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#define SSI_H_
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/*---------------------------------------------------------------------------*/
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/** \name Number of SSI instances supported by this CPU.
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* @{
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*/
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#define SSI_INSTANCE_COUNT 2
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name Base register memory locations.
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* @{
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@ -1,5 +1,9 @@
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/*
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* Copyright (c) 2013, University of Michigan.
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*
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* Copyright (c) 2015, Weptech elektronik GmbH
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* Author: Ulf Knoblich, ulf.knoblich@weptech.de
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -34,65 +38,144 @@
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* Header file for the cc2538 SPI driver, including macros for the
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* implementation of the low-level SPI primitives such as waiting for the TX
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* FIFO to be ready, inserting into the TX FIFO, etc.
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*
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* It supports the usage of SSI_NUM_INSTANCES instances by providing new
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* functions calls like
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*
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* - spix_init(uint8_t instance)
|
||||
* - spix_enable(uint8_t instance)
|
||||
* - spix_disable(uint8_t instance)
|
||||
* - spix_set_mode(unit8_t instance, ...)
|
||||
*
|
||||
* and new macros like
|
||||
*
|
||||
* - SPIX_WAITFORTxREADY(x)
|
||||
* - SPIX_WAITFOREOTx(x)
|
||||
* - SPIX_WAITFOREORx(x)
|
||||
* - SPIX_FLUSH(x)
|
||||
*
|
||||
* Some of the old functions and macros are still supported.
|
||||
* When using these deprecated functions, the SSI module to use
|
||||
* has to be be selected by means of the macro SPI_CONF_DEFAULT_INSTANCE.
|
||||
*
|
||||
* This SPI driver depends on the following defines:
|
||||
*
|
||||
* For the SSI0 module:
|
||||
*
|
||||
* - SPI0_CKL_PORT
|
||||
* - SPI0_CLK_PIN
|
||||
* - SPI0_TX_PORT
|
||||
* - SPI0_TX_PIN
|
||||
* - SPI0_RX_PORT
|
||||
* - SPI0_RX_PIN
|
||||
*
|
||||
* For the SSI1 module:
|
||||
*
|
||||
* - SPI1_CKL_PORT
|
||||
* - SPI1_CLK_PIN
|
||||
* - SPI1_TX_PORT
|
||||
* - SPI1_TX_PIN
|
||||
* - SPI1_RX_PORT
|
||||
* - SPI1_RX_PIN
|
||||
*/
|
||||
#ifndef SPI_ARCH_H_
|
||||
#define SPI_ARCH_H_
|
||||
|
||||
#include "contiki.h"
|
||||
|
||||
#include "dev/ssi.h"
|
||||
|
||||
#define SPI_WAITFORTxREADY() do { \
|
||||
while(!(REG(SSI0_BASE + SSI_SR) & SSI_SR_TNF)); \
|
||||
} while(0)
|
||||
|
||||
#define SPI_TXBUF REG(SSI0_BASE + SSI_DR)
|
||||
|
||||
#define SPI_RXBUF REG(SSI0_BASE + SSI_DR)
|
||||
|
||||
#define SPI_WAITFOREOTx() do { \
|
||||
while(REG(SSI0_BASE + SSI_SR) & SSI_SR_BSY); \
|
||||
} while(0)
|
||||
|
||||
#define SPI_WAITFOREORx() do { \
|
||||
while(!(REG(SSI0_BASE + SSI_SR) & SSI_SR_RNE)); \
|
||||
} while(0)
|
||||
|
||||
#ifdef SPI_FLUSH
|
||||
#error "You must include spi-arch.h before spi.h for the CC2538."
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* The SPI instance to use when using the deprecated SPI API. */
|
||||
#ifdef SPI_CONF_DEFAULT_INSTANCE
|
||||
#if SPI_CONF_DEFAULT_INSTANCE > (SSI_INSTANCE_COUNT - 1)
|
||||
#error Invalid SPI_CONF_DEFAULT_INSTANCE: valid values are 0 and 1
|
||||
#else
|
||||
#define SPI_DEFAULT_INSTANCE SPI_CONF_DEFAULT_INSTANCE
|
||||
#endif
|
||||
#define SPI_FLUSH() do { \
|
||||
while (REG(SSI0_BASE + SSI_SR) & SSI_SR_RNE) { \
|
||||
SPI_RXBUF; \
|
||||
#endif
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* Default values for the clock rate divider */
|
||||
#ifdef SPI0_CONF_CPRS_CPSDVSR
|
||||
#define SPI0_CPRS_CPSDVSR SPI0_CONF_CPRS_CPSDVSR
|
||||
#else
|
||||
#define SPI0_CPRS_CPSDVSR 2
|
||||
#endif
|
||||
|
||||
#ifdef SPI1_CONF_CPRS_CPSDVSR
|
||||
#define SPI1_CPRS_CPSDVSR SPI1_CONF_CPRS_CPSDVSR
|
||||
#else
|
||||
#define SPI1_CPRS_CPSDVSR 2
|
||||
#endif
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* New API macros */
|
||||
#define SPIX_WAITFORTxREADY(spi) do { \
|
||||
while(!(REG(CC_CONCAT3(SSI, spi, _BASE) + SSI_SR) & SSI_SR_TNF)) ; \
|
||||
} while(0)
|
||||
#define SPIX_BUF(spi) REG(CC_CONCAT3(SSI, spi, _BASE) + SSI_DR)
|
||||
#define SPIX_WAITFOREOTx(spi) do { \
|
||||
while(REG(CC_CONCAT3(SSI, spi, _BASE) + SSI_SR) & SSI_SR_BSY) ; \
|
||||
} while(0)
|
||||
#define SPIX_WAITFOREORx(spi) do { \
|
||||
while(!(REG(CC_CONCAT3(SSI, spi, _BASE) + SSI_SR) & SSI_SR_RNE)) ; \
|
||||
} while(0)
|
||||
#define SPIX_FLUSH(spi) do { \
|
||||
while(REG(CC_CONCAT3(SSI, spi, _BASE) + SSI_SR) & SSI_SR_RNE) { \
|
||||
SPIX_BUF(spi); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#define SPI_CS_CLR(port, pin) do { \
|
||||
#define SPIX_CS_CLR(port, pin) do { \
|
||||
GPIO_CLR_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin)); \
|
||||
} while(0)
|
||||
|
||||
#define SPI_CS_SET(port, pin) do { \
|
||||
#define SPIX_CS_SET(port, pin) do { \
|
||||
GPIO_SET_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin)); \
|
||||
} while(0)
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* Deprecated macros provided for compatibility reasons */
|
||||
#ifdef SPI_DEFAULT_INSTANCE
|
||||
#define SPI_WAITFORTxREADY() SPIX_WAITFORTxREADY(SPI_DEFAULT_INSTANCE)
|
||||
#define SPI_TXBUF SPIX_BUF(SPI_DEFAULT_INSTANCE)
|
||||
#define SPI_RXBUF SPI_TXBUF
|
||||
#define SPI_WAITFOREOTx() SPIX_WAITFOREOTx(SPI_DEFAULT_INSTANCE)
|
||||
#define SPI_WAITFOREORx() SPIX_WAITFOREORx(SPI_DEFAULT_INSTANCE)
|
||||
#ifdef SPI_FLUSH
|
||||
#error You must include spi-arch.h before spi.h for the CC2538
|
||||
#else
|
||||
#define SPI_FLUSH() SPIX_FLUSH(SPI_DEFAULT_INSTANCE)
|
||||
#endif
|
||||
#define SPI_CS_CLR(port, pin) SPIX_CS_CLR(port, pin)
|
||||
#define SPI_CS_SET(port, pin) SPIX_CS_SET(port, pin)
|
||||
#endif /* #ifdef SPI_DEFAULT_INSTANCE */
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** \name Arch-specific SPI functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Configure a GPIO to be the chip select pin
|
||||
* \brief Initialize the SPI bus for the instance given
|
||||
*
|
||||
* This sets the mode to Motorola SPI with the following format options:
|
||||
* Clock phase: 1; data captured on second (rising) edge
|
||||
* Clock polarity: 1; clock is high when idle
|
||||
* Data size: 8 bits
|
||||
*
|
||||
* Use spix_set_mode() to change the spi mode.
|
||||
*/
|
||||
void spi_cs_init(uint8_t port, uint8_t pin);
|
||||
|
||||
/** \brief Enables the SPI peripheral
|
||||
*/
|
||||
void spi_enable(void);
|
||||
|
||||
/** \brief Disables the SPI peripheral
|
||||
* \note Call this function to save power when the SPI is unused.
|
||||
*/
|
||||
void spi_disable(void);
|
||||
void spix_init(uint8_t spi);
|
||||
|
||||
/**
|
||||
* \brief Configure the SPI data and clock polarity and the data size.
|
||||
* \brief Enables the SPI peripheral for the instance given
|
||||
*/
|
||||
void spix_enable(uint8_t spi);
|
||||
|
||||
/**
|
||||
* \brief Disables the SPI peripheral for the instance given
|
||||
* \note Call this function to save power when the SPI is unused.
|
||||
*/
|
||||
void spix_disable(uint8_t spi);
|
||||
|
||||
/**
|
||||
* \brief Configure the SPI data and clock polarity and the data size for the
|
||||
* instance given
|
||||
*
|
||||
* This function configures the SSI peripheral to use a particular SPI
|
||||
* configuration that a slave device requires. It should always be called
|
||||
|
|
@ -100,6 +183,7 @@ void spi_disable(void);
|
|||
*
|
||||
* See section 19.4.4 in the CC2538 user guide for more information.
|
||||
*
|
||||
* \param spi The SSI instance to use.
|
||||
* \param frame_format Set the SSI frame format. Use SSI_CR0_FRF_MOTOROLA,
|
||||
* SSI_CR0_FRF_TI, or SSI_CR0_FRF_MICROWIRE.
|
||||
* \param clock_polarity In Motorola mode, set whether the clock is high or low
|
||||
|
|
@ -109,8 +193,17 @@ void spi_disable(void);
|
|||
* \param data_size The number of bits in each "byte" of data. Must be
|
||||
* between 4 and 16, inclusive.
|
||||
*/
|
||||
void spi_set_mode(uint32_t frame_format, uint32_t clock_polarity,
|
||||
uint32_t clock_phase, uint32_t data_size);
|
||||
void spix_set_mode(uint8_t spi, uint32_t frame_format,
|
||||
uint32_t clock_polarity, uint32_t clock_phase,
|
||||
uint32_t data_size);
|
||||
|
||||
/**
|
||||
* \brief Configure a GPIO to be the chip select pin.
|
||||
*
|
||||
* Even if this function does not depend on the SPI instance used, we rename
|
||||
* it to reflect the new naming convention.
|
||||
*/
|
||||
void spix_cs_init(uint8_t port, uint8_t pin);
|
||||
|
||||
/** @} */
|
||||
|
||||
|
|
|
|||
|
|
@ -184,15 +184,41 @@
|
|||
/**
|
||||
* \name SPI configuration
|
||||
*
|
||||
* These values configure which CC2538 pins to use for the SPI lines.
|
||||
* These values configure which CC2538 pins to use for the SPI lines. Both
|
||||
* SPI instances can be used independently by providing the corresponding
|
||||
* port / pin macros.
|
||||
* @{
|
||||
*/
|
||||
#define SPI_CLK_PORT GPIO_A_NUM /**< Clock port */
|
||||
#define SPI_CLK_PIN 2 /**< Clock pin */
|
||||
#define SPI_MOSI_PORT GPIO_A_NUM /**< MOSI port */
|
||||
#define SPI_MOSI_PIN 4 /**< MOSI pin */
|
||||
#define SPI_MISO_PORT GPIO_A_NUM /**< MISO port */
|
||||
#define SPI_MISO_PIN 5 /**< MISO pin */
|
||||
#define SPI0_IN_USE 0
|
||||
#define SPI1_IN_USE 0
|
||||
#if SPI0_IN_USE
|
||||
/** Clock port SPI0 */
|
||||
#define SPI0_CLK_PORT GPIO_A_NUM
|
||||
/** Clock pin SPI0 */
|
||||
#define SPI0_CLK_PIN 2
|
||||
/** TX port SPI0 (master mode: MOSI) */
|
||||
#define SPI0_TX_PORT GPIO_A_NUM
|
||||
/** TX pin SPI0 */
|
||||
#define SPI0_TX_PIN 4
|
||||
/** RX port SPI0 (master mode: MISO */
|
||||
#define SPI0_RX_PORT GPIO_A_NUM
|
||||
/** RX pin SPI0 */
|
||||
#define SPI0_RX_PIN 5
|
||||
#endif /* #if SPI0_IN_USE */
|
||||
#if SPI1_IN_USE
|
||||
/** Clock port SPI1 */
|
||||
#define SPI1_CLK_PORT GPIO_A_NUM
|
||||
/** Clock pin SPI1 */
|
||||
#define SPI1_CLK_PIN 2
|
||||
/** TX port SPI1 (master mode: MOSI) */
|
||||
#define SPI1_TX_PORT GPIO_A_NUM
|
||||
/** TX pin SPI1 */
|
||||
#define SPI1_TX_PIN 4
|
||||
/** RX port SPI1 (master mode: MISO) */
|
||||
#define SPI1_RX_PORT GPIO_A_NUM
|
||||
/** RX pin SPI1 */
|
||||
#define SPI1_RX_PIN 5
|
||||
#endif /* #if SPI1_IN_USE */
|
||||
/** @} */
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in a new issue