Reincarnate the sensinode/cc2430 port
This commit is contained in:
George Oikonomou
parent
c78b5bad5c
commit
b7674c3636
114 changed files with 10044 additions and 3068 deletions
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@ -1,216 +1,69 @@
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/**
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* \file
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* DMA driver
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* Driver for the cc2430 DMA controller. Can be assigned to any bank
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*
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* \author
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* Original: Martti Huttunen <martti@sensinode.com>
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* Port: Zach Shelby <zach@sensinode.com>
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* Further Modifications:
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* George Oikonomou <oikonomou@users.sourceforge.net>
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*
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* bankable DMA functions
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*/
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#include <stdio.h>
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#include "contiki.h"
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#include "banked.h"
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#include "dev/dma.h"
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#include "cc2430_sfr.h"
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dma_config_t dma_conf[4];
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struct process * dma_callback[4];
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#if DMA_ON
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struct dma_config dma_conf[DMA_CHANNEL_COUNT]; /* DMA Descriptors */
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struct process * dma_callback[DMA_CHANNEL_COUNT];
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/*---------------------------------------------------------------------------*/
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void
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dma_init(void) __banked
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dma_init(void)
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{
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uint16_t tmp_ptr;
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memset(dma_conf, 0, 4*sizeof(dma_config_t));
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for(tmp_ptr = 0; tmp_ptr < 4; tmp_ptr++) {
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memset(dma_conf, 0, 4 * sizeof(dma_config_t));
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for(tmp_ptr = 0; tmp_ptr < DMA_CHANNEL_COUNT; tmp_ptr++) {
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dma_callback[tmp_ptr] = 0;
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}
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tmp_ptr = (uint16_t) &(dma_conf[0]);
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/* The address of the descriptor for Channel 0 is configured separately */
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tmp_ptr = (uint16_t) &(dma_conf[0]);
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DMA0CFGH = tmp_ptr >> 8;
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DMA0CFGL = tmp_ptr;
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/*
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* Descriptors for Channels 1-4 must be consecutive in RAM.
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* We write the address of the 1st one to the register and the rest are
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* derived by the SoC
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*/
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#if (DMA_CHANNEL_COUNT > 1)
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tmp_ptr = (uint16_t) &(dma_conf[1]);
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DMA1CFGH = tmp_ptr >> 8;
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DMA1CFGL = tmp_ptr;
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IEN1_DMAIE = 1; /*enable DMA interrupts*/
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}
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/*---------------------------------------------------------------------------*/
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#ifdef HAVE_DMA
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/**
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* Configure a DMA channel except word mode.
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*
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* \param channel channel ID;
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* \param src source address;
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* \param src_inc source increment mode;
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* \param dst dest address;
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* \param dst_inc dest increment mode;
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* \param length maximum length;
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* \param vlen_mode variable length mode;
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* \param t_mode DMA transfer mode;
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* \param trigger DMA trigger;
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* \param proc process that is upon interrupt;
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*
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* \return Handle to DMA channel
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* \return 0 invalid channel
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*/
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/* IMPLEMENTED dma_config as macro to reduce stack/code space
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xDMAHandle
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dma_config(uint8_t channel, void *src, dma_inc_t src_inc, void *dst, dma_inc_t dst_inc,
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uint16_t length, dma_vlen_t vlen_mode, dma_type_t t_mode, dma_trigger_t trigger,
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struct process * proc) __banked
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{
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return dma_config2(channel,src,src_inc, dst, dst_inc, length, 0, vlen_mode, t_mode, trigger, proc);
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}
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*/
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/*---------------------------------------------------------------------------*/
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/**
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* Configure a DMA channel.
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*
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* \param channel channel ID;
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* \param src source address;
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* \param src_inc source increment mode;
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* \param dst dest address;
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* \param dst_inc dest increment mode;
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* \param length maximum length;
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* \param word_mode set to 1 for 16-bits per transfer;
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* \param vlen_mode variable length mode;
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* \param t_mode DMA transfer mode;
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* \param trigger DMA trigger;
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* \param proc process that is upon interrupt;
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*
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* \return Handle to DMA channel
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* \return 0 invalid channel
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*/
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xDMAHandle
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dma_config2(uint8_t channel, void *src, dma_inc_t src_inc, void *dst, dma_inc_t dst_inc,
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uint16_t length, uint8_t word_mode, dma_vlen_t vlen_mode, dma_type_t t_mode, dma_trigger_t trigger,
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struct process * proc) __banked
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{
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unsigned char jj;
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if((!channel) || (channel > 4)) {
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return 0;
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}
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#endif
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DMAIRQ &= ~(1 << channel);
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channel--;
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dma_conf[channel].src_h = ((uint16_t) src) >> 8;
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dma_conf[channel].src_l = ((uint16_t) src);
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dma_conf[channel].dst_h = ((uint16_t) dst) >> 8;
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dma_conf[channel].dst_l = ((uint16_t) dst);
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dma_conf[channel].len_h = vlen_mode + (length >> 8);
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dma_conf[channel].len_l = length;
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dma_conf[channel].t_mode = ((word_mode&0x1)<<7) | (t_mode << 5) | trigger;
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dma_conf[channel].addr_mode = (src_inc << 6) + (dst_inc << 4) + 2; /*DMA has priority*/
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/*Callback is defined*/
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if(proc) {
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dma_conf[channel].addr_mode |= 8; /*set IRQMASK*/
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IEN1_DMAIE = 1; /*enable DMA interrupts*/
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}
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dma_callback[channel] = proc;
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return (xDMAHandle)channel + 1;
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IEN1_DMAIE = 1; /* Enable DMA interrupts */
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Arm a DMA channel.
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*
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* \param channel channel handle;
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*
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* \return pdTRUE
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* \return pdFALSE semaphore creation failed
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/*
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* Associate process p with DMA channel c. When a transfer on that channel
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* completes, the ISR will poll this process.
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*/
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uint8_t
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dma_arm(xDMAHandle channel) __banked
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{
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uint8_t ch_id = ((uint8_t)channel);
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if(!ch_id || (ch_id > 4)) {
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return 0;
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}
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DMAARM |= (1 << ch_id);
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return 1;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Stop a DMA channel.
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*
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* \param channel channel handle;
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*
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* \return pdTRUE
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* \return pdFALSE semaphore creation failed
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*/
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uint8_t
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dma_abort(xDMAHandle channel) __banked
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{
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uint8_t ch_id = ((uint8_t) channel);
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if(!ch_id || (ch_id > 4)) {
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return 0;
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}
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DMAARM = 0x80 + (1 << ch_id); /*ABORT + channel bit*/
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return 1;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Trigger a DMA channel.
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*
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* \param channel channel handle;
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*
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* \return pdTRUE
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* \return pdFALSE semaphore creation failed
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*/
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uint8_t
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dma_trigger(xDMAHandle channel) __banked
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{
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uint8_t ch_id = ((uint8_t) channel);
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if(!ch_id || (ch_id > 4)) {
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return 0;
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}
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DMAREQ |= (1 << ch_id);
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return 1;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* Get DMA state.
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*
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* \param channel channel handle;
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*
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* \return pdTRUE active
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* \return pdFALSE not active
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*/
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uint8_t
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dma_state(xDMAHandle channel) __banked
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{
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uint8_t ch_id = ((uint8_t)channel);
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if(!ch_id || (ch_id > 4)) {
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return 0;
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}
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if((DMAIRQ &(1 << ch_id)) == 0) {
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return 1;
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}
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return 0;
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}
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/*---------------------------------------------------------------------------*/
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void
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dma_config_print(xDMAHandle channel) __banked
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dma_associate_process(struct process * p, uint8_t c)
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{
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uint8_t ch_id = channel - 1;
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if(ch_id > 4) {
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if((!c) || (c >= DMA_CHANNEL_COUNT)) {
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return;
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}
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printf("DMA channel %d @ %x %x ", ch_id, (uint16_t) &(dma_conf[ch_id]) >> 8, (uint16_t) &(dma_conf[ch_id]) & 0xFF);
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{
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uint8_t i;
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uint8_t *ptr = (uint8_t *)&(dma_conf[ch_id]);
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for(i = 0; i< 8; i++) {
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if(i != 0) {
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printf(":%02x", *ptr++);
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}
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}
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printf("\n");
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if(p) {
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dma_conf[c].inc_prio |= 8; /* Enable interrupt generation */
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IEN1_DMAIE = 1; /* Make sure DMA interrupts are acknowledged */
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}
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dma_callback[c] = p;
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}
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/*---------------------------------------------------------------------------*/
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#endif
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