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cc2538: spi: Add format configuration options

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Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau 2013-11-04 18:39:52 +01:00
parent f1ca1b742c
commit b134e35450
1 changed files with 21 additions and 3 deletions
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24
cpu/cc2538/dev/spi.c
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@ -42,6 +42,21 @@
#include "dev/ssi.h" #include "dev/ssi.h"
#include "dev/gpio.h" #include "dev/gpio.h"
/* Default: Motorola mode 3 with 8-bit data words */
#ifndef SPI_CONF_PHASE
#define SPI_CONF_PHASE SSI_CR0_SPH
#endif
#ifndef SPI_CONF_POLARITY
#define SPI_CONF_POLARITY SSI_CR0_SPO
#endif
#ifndef SPI_CONF_DATA_SIZE
#define SPI_CONF_DATA_SIZE 8
#endif
#if SPI_CONF_DATA_SIZE < 4 || SPI_CONF_DATA_SIZE > 16
#error SPI_CONF_DATA_SIZE must be set between 4 and 16 inclusive.
#endif
/** /**
* \brief Initialize the SPI bus. * \brief Initialize the SPI bus.
* *
@ -51,7 +66,10 @@
* CC2538_SPI_MISO_PORT_NUM CC2538_SPI_MISO_PIN_NUM * CC2538_SPI_MISO_PORT_NUM CC2538_SPI_MISO_PIN_NUM
* CC2538_SPI_SEL_PORT_NUM CC2538_SPI_SEL_PIN_NUM * CC2538_SPI_SEL_PORT_NUM CC2538_SPI_SEL_PIN_NUM
* *
* This sets the SPI data width to 8 bits and the mode to Freescale mode 3. * This sets the mode to Motorola SPI with the following format options:
* SPI_CONF_PHASE: 0 or SSI_CR0_SPH
* SPI_CONF_POLARITY: 0 or SSI_CR0_SPO
* SPI_CONF_DATA_SIZE: 4 to 16 bits
*/ */
void void
spi_init(void) spi_init(void)
@ -86,8 +104,8 @@ spi_init(void)
/* Configure the clock */ /* Configure the clock */
REG(SSI0_BASE + SSI_CPSR) = 2; REG(SSI0_BASE + SSI_CPSR) = 2;
/* Put the ssi in motorola SPI mode with 8 bit data */ /* Put the ssi in Motorola SPI mode using the provided format options */
REG(SSI0_BASE + SSI_CR0) = SSI_CR0_SPH_M | SSI_CR0_SPO_M | (7); REG(SSI0_BASE + SSI_CR0) = SPI_CONF_PHASE | SPI_CONF_POLARITY | (SPI_CONF_DATA_SIZE - 1);
/* Enable the SSI */ /* Enable the SSI */
REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE; REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE;