Fixing more possible out of date files.
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c_oflynn
parent
15ba03fea5
commit
a73ed65dac
7 changed files with 88 additions and 91 deletions
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@ -2,12 +2,12 @@
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* All rights reserved.
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*
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* Additional fixes for AVR contributed by:
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* Colin O'Flynn coflynn@newae.com
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* Eric Gnoske egnoske@gmail.com
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* Blake Leverett bleverett@gmail.com
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* Mike Vidales mavida404@gmail.com
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* Kevin Brown kbrown3@uccs.edu
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* Nate Bohlmann nate@elfwerks.com
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* Colin O'Flynn coflynn@newae.com
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* Eric Gnoske egnoske@gmail.com
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* Blake Leverett bleverett@gmail.com
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* Mike Vidales mavida404@gmail.com
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* Kevin Brown kbrown3@uccs.edu
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* Nate Bohlmann nate@elfwerks.com
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*
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* All rights reserved.
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*
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@ -36,7 +36,7 @@
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: radio.c,v 1.1 2008/10/14 09:43:40 adamdunkels Exp $
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* $Id: radio.c,v 1.2 2008/10/14 18:37:28 c_oflynn Exp $
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*/
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/**
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@ -113,8 +113,7 @@ static uint8_t rssi_val;
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static uint8_t rx_mode;
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uint8_t rxMode = RX_AACK_ON;
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static hal_rx_frame_t rx_frame;
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parsed_frame_t parsed_frame;
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static parsed_frame_t parsed_frame;
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/*============================ PROTOTYPES ====================================*/
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bool radio_is_sleeping(void);
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@ -185,8 +184,8 @@ radio_init(bool cal_rc_osc,
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else {
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if (hal_register_read(RG_MAN_ID_0) != SUPPORTED_MANUFACTURER_ID)
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init_status = RADIO_UNSUPPORTED_DEVICE;
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else
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hal_register_write(RG_IRQ_MASK, RF230_SUPPORTED_INTERRUPT_MASK);
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else
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hal_register_write(RG_IRQ_MASK, RF230_SUPPORTED_INTERRUPT_MASK);
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}
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}
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@ -202,6 +201,19 @@ radio_init(bool cal_rc_osc,
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return init_status;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t *
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radio_frame_data(void)
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{
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return rx_frame.data;
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}
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uint8_t
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radio_frame_length(void)
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{
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return rx_frame.length;
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}
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/*---------------------------------------------------------------------------*/
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static void
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radio_rx_start_event(uint32_t const isr_timestamp, uint8_t const frame_length)
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@ -236,10 +248,10 @@ radio_trx_end_event(uint32_t const isr_timestamp)
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/* radio has received frame, store it away */
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parsed_frame.time = isr_timestamp;
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parsed_frame.rssi = rssi_val;
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hal_frame_read(&rx_frame, NULL);
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rx_frame_parse(&rx_frame, &parsed_frame);
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}
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}
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if (!rx_mode){
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/* Put radio back into receive mode. */
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@ -594,23 +606,23 @@ radio_get_clock_speed(void)
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radio_status_t
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radio_set_clock_speed(bool direct, uint8_t clock_speed)
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{
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/*Check function parameter and current clock speed.*/
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/*Check function parameter and current clock speed.*/
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if (clock_speed > CLKM_16MHZ){
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return RADIO_INVALID_ARGUMENT;
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return RADIO_INVALID_ARGUMENT;
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}
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if (radio_get_clock_speed() == clock_speed){
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return RADIO_SUCCESS;
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}
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/*Select to change the CLKM frequency directly or after returning from SLEEP.*/
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/*Select to change the CLKM frequency directly or after returning from SLEEP.*/
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if (direct == false){
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hal_subregister_write(SR_CLKM_SHA_SEL, 1);
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hal_subregister_write(SR_CLKM_SHA_SEL, 1);
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} else {
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hal_subregister_write(SR_CLKM_SHA_SEL, 0);
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hal_subregister_write(SR_CLKM_SHA_SEL, 0);
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}
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hal_subregister_write(SR_CLKM_CTRL, clock_speed);
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hal_subregister_write(SR_CLKM_CTRL, clock_speed);
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return RADIO_SUCCESS;
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}
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@ -776,6 +788,8 @@ bool radio_is_sleeping(void)
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radio_status_t
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radio_set_trx_state(uint8_t new_state)
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{
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uint8_t original_state;
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/*Check function paramter and current state of the radio transceiver.*/
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if (!((new_state == TRX_OFF) ||
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(new_state == RX_ON) ||
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@ -789,19 +803,22 @@ radio_set_trx_state(uint8_t new_state)
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return RADIO_WRONG_STATE;
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}
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uint8_t original_state = radio_get_trx_state();
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if ((original_state == BUSY_RX) ||
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(original_state == BUSY_TX) ||
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(original_state == BUSY_RX_AACK) ||
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(original_state == BUSY_TX_ARET)){
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return RADIO_BUSY_STATE;
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// Wait for radio to finish previous operation
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for(;;)
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{
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original_state = radio_get_trx_state();
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if (original_state != BUSY_TX_ARET &&
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original_state != BUSY_RX_AACK &&
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original_state != BUSY_RX &&
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original_state != BUSY_TX)
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break;
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}
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if (new_state == original_state){
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return RADIO_SUCCESS;
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}
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/* At this point it is clear that the requested new_state is: */
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/* TRX_OFF, RX_ON, PLL_ON, RX_AACK_ON or TX_ARET_ON. */
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@ -849,7 +866,7 @@ radio_set_trx_state(uint8_t new_state)
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rx_mode = true;
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} else {
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rx_mode = false;
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}
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}
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}
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return set_state_status;
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@ -1190,7 +1207,7 @@ radio_configure_csma(uint8_t seed0, uint8_t be_csma_seed1)
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bool
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calibrate_rc_osc_clkm(void)
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{
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bool success = false;
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bool success = false;
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/* Use the 1 MHz CLK_M from the AT86RF230. */
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uint16_t temp, counter;
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@ -1204,72 +1221,72 @@ calibrate_rc_osc_clkm(void)
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#define TARGETVAL ((1000000ULL * 256 * 32) / F_CPU)
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osccal_saved = OSCCAL;
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cli();
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osccal_saved = OSCCAL;
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cli();
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radio_set_clock_speed(true, CLKM_1MHz);
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radio_set_clock_speed(true, CLKM_1MHz);
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/* Save current values of timer status. */
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tccr2b = TCCR2B;
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tccr1b = TCCR1B;
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tccr1a = TCCR1A;
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tccr2b = TCCR2B;
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tccr1b = TCCR1B;
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tccr1a = TCCR1A;
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/* Stop timers 1 and 2. */
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/* Set timer 1 to normal mode (no CTC, no PWM, just count). */
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TCCR2B = 0;
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TCCR1B = 0;
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TCCR1A = 0;
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TCCR2B = 0;
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TCCR1B = 0;
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TCCR1A = 0;
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for (counter = 0; counter < 1000; counter++){
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/* Delete pending timer 1 and 2 interrupts, and clear the */
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/* counters. */
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TIFR1 = 0xFF;
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TIFR2 = 0xFF;
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TCNT2 = 0;
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TCNT1 = 0;
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TIFR1 = 0xFF;
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TIFR2 = 0xFF;
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TCNT2 = 0;
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TCNT1 = 0;
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/* Timer 2 driven from clock divided by 32 */
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TCCR2B = (1 << CS21) | (1 << CS20);
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TCCR2B = (1 << CS21) | (1 << CS20);
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/* Timer 1 driven with external clock */
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TCCR1B = (1 << CS12) | (1 << CS11);
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TCCR1B = (1 << CS12) | (1 << CS11);
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/* Wait for timer 2 to overflow. */
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while (!(TIFR2 & (1 << TOV2))){
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;
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;
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}
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/* Stop timer 1. Now, TCNT1 contains the number of CPU cycles */
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/* counted while timer 2 was counting */
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TCCR1B = 0;
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TCCR2B = 0;
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TCCR1B = 0;
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TCCR2B = 0;
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temp = TCNT1;
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temp = TCNT1;
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if (temp < (uint16_t)(0.995 * TARGETVAL)){
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/* Too fast, slow down */
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OSCCAL--;
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OSCCAL--;
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} else if (temp > (uint16_t)(1.005 * TARGETVAL)){
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/* Too slow, speed up */
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OSCCAL++;
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OSCCAL++;
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} else {
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/* We are within +/- 0.5 % of our target frequency, so we're */
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/* done. */
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success = true;
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break;
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success = true;
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break;
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}
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}
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}
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radio_set_clock_speed(true, CLKM_DISABLED);
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radio_set_clock_speed(true, CLKM_DISABLED);
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/* restore timer status regs */
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TCCR2B = tccr2b;
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TCCR1B = tccr1b;
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TCCR1A = tccr1a;
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TCCR2B = tccr2b;
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TCCR1B = tccr1b;
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TCCR1A = tccr1a;
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if (!success){
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/* We failed, therefore restore previous OSCCAL value. */
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OSCCAL = osccal_saved;
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}
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OSCCAL = osccal_saved;
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}
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return success;
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return success;
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}
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/*----------------------------------------------------------------------------*/
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@ -1293,7 +1310,7 @@ calibrate_rc_osc_32k(void)
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*/
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uint8_t osccal_original = OSCCAL;
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volatile uint16_t temp;
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/* This is bad practice, but seems to work. */
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OSCCAL = 0x80;
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@ -1331,7 +1348,7 @@ calibrate_rc_osc_32k(void)
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*/
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while (!(TIFR2 & (1 << TOV2))){
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;
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}
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}
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temp = TCNT1;
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TCCR1B = 0;
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