Enhanced Ethernet drivers.
Made Ethernet drivers easier to consume by assembly programs. * Replaced function pointers with JMP instructions. * Provide return values additionally via Carry flag. Reset Ethernet chips on initialization. Both for the CS8900A and the W5100 the data sheets just say that the RESET bit is automatically cleared after the RESET. This may be interpreted in two ways: 1) There's no need to be afraid of reading the RESET bit as 1 and unintentionally trigger a RESET by writing it back after ORing in some other bit. 2) The RESET process isn't complete before the RESET bit hasn't become 0 again. It's impossible for me to empirically falsify the latter option as the drivers are supposed to work on faster machines than the ones I have access to. And if the RESET process includes things like oscillators then the time to complete the RESET could differ even between multiple exemplars of the same chip. Therefore I opted to presume the latter option. However that means a non-exsistent chip may cause an infinite loop while waiting for the RESET bit to be cleared so I finally added code to detect the presence of the Ethernet chips. There's a risk of a chip being locked up in a way that makes the detection fail - and therefore the RESET not being performed. This catch-22 needs to be solved by the user doing a hard RESET.
This commit is contained in:
Oliver Schmidt
parent
a0961fc3c4
commit
a5d7a06027
4 changed files with 177 additions and 109 deletions
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@ -48,10 +48,10 @@ bufaddr:.res 2 ; Address
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bufsize:.res 2 ; Size
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; Jump table.
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.addr init
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.addr poll
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.addr send
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.addr exit
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jmp init
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jmp poll
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jmp send
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jmp exit
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;---------------------------------------------------------------------
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@ -85,6 +85,8 @@ fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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.byte fixup14-fixup13, fixup15-fixup14, fixup16-fixup15
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.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
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.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
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.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
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.byte fixup26-fixup25
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fixups = * - fixup
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@ -143,6 +145,29 @@ fixup01:lda isq+1
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ora #$01 ; Set clockport bit
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fixup02:sta isq+1
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; Check EISA registration number of Crystal Semiconductor
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; PACKETPP = $0000, PPDATA == $630E ?
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lda #$00
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tax
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jsr packetpp_ax
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lda #$63^$0E
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fixup03:eor ppdata
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fixup04:eor ppdata+1
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beq :+
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sec
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rts
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; Initiate a chip-wide reset
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; PACKETPP = $0114, PPDATA = $0040
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: lda #$14
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jsr packetpp_a1
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ldy #$40
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fixup05:sty ppdata
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: jsr packetpp_a1
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fixup06:ldy ppdata
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and #$40
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bne :-
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; Accept valid unicast + broadcast frames
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; PACKETPP = $0104, PPDATA = $0D05
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lda #$04
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@ -173,6 +198,8 @@ fixup02:sta isq+1
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lda #$D3
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ldx #$00
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jsr ppdata_ax
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txa
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clc
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rts
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;---------------------------------------------------------------------
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@ -183,27 +210,22 @@ poll:
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; PACKETPP = $0124, PPDATA & $0D00 ?
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lda #$24
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jsr packetpp_a1
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fixup03:lda ppdata+1
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fixup07:lda ppdata+1
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and #$0D
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bne :+
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; No frame ready
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tax
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rts
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beq :+
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; Process the incoming frame
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; --------------------------
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; Read receiver event and discard it
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; RXTXREG
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:
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fixup04:ldx rxtxreg+1
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fixup05:lda rxtxreg
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fixup08:ldx rxtxreg+1
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fixup09:lda rxtxreg
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; Read frame length
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; cnt = len = RXTXREG
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fixup06:ldx rxtxreg+1
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fixup07:lda rxtxreg
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fixup10:ldx rxtxreg+1
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fixup11:lda rxtxreg
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sta len
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stx len+1
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sta cnt
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@ -217,23 +239,24 @@ fixup07:lda rxtxreg
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cmp cnt
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lda bufsize+1
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sbc cnt+1
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bcs :+
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bcs :++
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; Yes, skip frame
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jsr skipframe
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; No frame ready
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lda #$00
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tax
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: tax
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sec
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rts
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; Read bytes into buffer
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: jsr adjustptr
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:
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fixup08:lda rxtxreg
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fixup12:lda rxtxreg
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sta (ptr),y
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iny
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fixup09:lda rxtxreg+1
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fixup13:lda rxtxreg+1
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sta (ptr),y
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iny
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bne :-
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@ -244,6 +267,7 @@ fixup09:lda rxtxreg+1
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; Return frame length
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lda len
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ldx len+1
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clc
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rts
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;---------------------------------------------------------------------
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@ -256,12 +280,12 @@ send:
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; Transmit command
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lda #$C9
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ldx #$00
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fixup10:sta txcmd
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fixup11:stx txcmd+1
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fixup14:sta txcmd
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fixup15:stx txcmd+1
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lda cnt
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ldx cnt+1
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fixup12:sta txlen
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fixup13:stx txlen+1
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fixup16:sta txlen
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fixup17:stx txlen+1
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; Adjust odd frame length
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jsr adjustcnt
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@ -273,7 +297,7 @@ fixup13:stx txlen+1
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; PACKETPP = $0138, PPDATA & $0100 ?
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: lda #$38
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jsr packetpp_a1
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fixup14:lda ppdata+1
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fixup18:lda ppdata+1
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and #$01
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bne :+
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@ -283,6 +307,7 @@ fixup14:lda ppdata+1
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; And try again
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dey
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bne :-
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sec
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rts
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; Send the frame
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@ -291,15 +316,16 @@ fixup14:lda ppdata+1
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; Write bytes from buffer
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: jsr adjustptr
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: lda (ptr),y
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fixup15:sta rxtxreg
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fixup19:sta rxtxreg
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iny
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lda (ptr),y
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fixup16:sta rxtxreg+1
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fixup20:sta rxtxreg+1
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iny
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bne :-
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inc ptr+1
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dex
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bpl :-
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clc
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rts
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;---------------------------------------------------------------------
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@ -311,15 +337,16 @@ exit:
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packetpp_a1:
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ldx #$01
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fixup17:sta packetpp
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fixup18:stx packetpp+1
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packetpp_ax:
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fixup21:sta packetpp
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fixup22:stx packetpp+1
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rts
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;---------------------------------------------------------------------
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ppdata_ax:
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fixup19:sta ppdata
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fixup20:stx ppdata+1
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fixup23:sta ppdata
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fixup24:stx ppdata+1
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rts
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;---------------------------------------------------------------------
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@ -328,9 +355,9 @@ skipframe:
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; PACKETPP = $0102, PPDATA = PPDATA | $0040
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lda #$02
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jsr packetpp_a1
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fixup21:lda ppdata
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fixup25:lda ppdata
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ora #$40
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fixup22:sta ppdata
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fixup26:sta ppdata
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rts
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;---------------------------------------------------------------------
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@ -47,9 +47,13 @@ struct {
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struct uip_eth_addr ethernet_address;
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uint8_t *buffer;
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uint16_t buffer_size;
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void __fastcall__ (* init)(uint16_t reg);
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char jmp_init;
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char __fastcall__ (* init)(uint16_t reg);
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char jmp_poll;
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uint16_t (* poll)(void);
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char jmp_send;
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void __fastcall__ (* send)(uint16_t len);
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char jmp_exit;
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void (* exit)(void);
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} *module;
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@ -97,7 +101,10 @@ ethernet_init(struct ethernet_config *config)
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module->buffer = uip_buf;
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module->buffer_size = UIP_BUFSIZE;
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module->init(config->addr);
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if(module->init(config->addr)) {
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log_message(config->name, ": No hardware");
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error_exit();
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}
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uip_setethaddr(module->ethernet_address);
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}
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@ -49,10 +49,10 @@ bufaddr:.res 2 ; Address
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bufsize:.res 2 ; Size
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; Jump table.
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.addr init
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.addr poll
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.addr send
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.addr exit
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jmp init
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jmp poll
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jmp send
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jmp exit
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;---------------------------------------------------------------------
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@ -89,7 +89,7 @@ fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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.byte fixup29-fixup28, fixup30-fixup29, fixup31-fixup30
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.byte fixup32-fixup31, fixup33-fixup32, fixup34-fixup33
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.byte fixup35-fixup34, fixup36-fixup35, fixup37-fixup36
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.byte fixup38-fixup37
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.byte fixup38-fixup37, fixup39-fixup38, fixup40-fixup39
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fixups = * - fixup
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@ -195,51 +195,58 @@ fixup06:stx ethrcr+1
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lda #$01 ; Bank 1
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fixup07:sta ethbsr
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fixup08:lda ethcr+1
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; Check ISA mode base address register for reset values
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lda #$18^67 ; I/O base $300 + ROM $CC000
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fixup08:eor ethbar
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fixup09:eor ethbar+1
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beq :+
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sec
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rts
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:
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fixup10:lda ethcr+1
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ora #%00010000 ; No wait (IOCHRDY)
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fixup09:sta ethcr+1
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fixup11:sta ethcr+1
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lda #%00001001 ; Auto release
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fixup10:sta ethctr+1
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fixup12:sta ethctr+1
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; Set MAC address
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ldy #$00
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: lda mac,y
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fixup11:sta ethiar,y
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fixup13:sta ethiar,y
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iny
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cpy #$06
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bcc :-
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; Set interrupt mask
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lda #$02 ; Bank 2
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fixup12:sta ethbsr
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fixup14:sta ethbsr
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lda #%00000000 ; No interrupts
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fixup13:sta ethmsk
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fixup15:sta ethmsk
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tax
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clc
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rts
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;---------------------------------------------------------------------
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poll:
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fixup14:lda ethist
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fixup16:lda ethist
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and #%00000001 ; RCV INT
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bne :+
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; No packet available
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tax
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rts
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beq :+
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; Process the incoming packet
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; ---------------------------
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: lda #$00
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lda #$00
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ldx #%11100000 ; RCV, AUTO INCR., READ
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fixup15:sta ethptr
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fixup16:stx ethptr+1
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fixup17:sta ethptr
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fixup18:stx ethptr+1
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; Last word contains 'last data byte' and $60 or 'fill byte' and $40
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fixup17:lda ethdata ; Status word
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fixup18:lda ethdata ; Need high byte only
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fixup19:lda ethdata ; Status word
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fixup20:lda ethdata ; Need high byte only
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; Move ODDFRM bit into carry:
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; - Even packet length -> carry clear -> subtract 6 bytes
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@ -251,10 +258,10 @@ fixup18:lda ethdata ; Need high byte only
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lsr
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; The packet contains 3 extra words
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fixup19:lda ethdata ; Total number of bytes
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fixup21:lda ethdata ; Total number of bytes
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sbc #$05 ; Actually 5 or 6 depending on carry
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sta len
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fixup20:lda ethdata
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fixup22:lda ethdata
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sbc #$00
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sta len+1
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@ -263,22 +270,23 @@ fixup20:lda ethdata
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cmp len
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lda bufsize+1
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sbc len+1
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bcs :+
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bcs :++
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; Yes, skip packet
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; Remove and release RX packet from the FIFO
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lda #%10000000
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fixup21:sta ethmmucr
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fixup23:sta ethmmucr
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; No packet available
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lda #$00
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tax
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: tax
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sec
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rts
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; Read bytes into buffer
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: jsr adjustptr
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:
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fixup22:lda ethdata
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fixup24:lda ethdata
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sta (ptr),y
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iny
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bne :-
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@ -288,11 +296,12 @@ fixup22:lda ethdata
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; Remove and release RX packet from the FIFO
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lda #%10000000
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fixup23:sta ethmmucr
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fixup25:sta ethmmucr
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; Return packet length
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lda len
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ldx len+1
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clc
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rts
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;---------------------------------------------------------------------
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@ -305,14 +314,14 @@ send:
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; Allocate memory for TX
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txa
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ora #%00100000
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fixup24:sta ethmmucr
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fixup26:sta ethmmucr
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; 8 retries
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ldy #$08
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; Wait for allocation ready
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:
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fixup25:lda ethist
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fixup27:lda ethist
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and #%00001000 ; ALLOC INT
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bne :+
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@ -322,25 +331,26 @@ fixup25:lda ethist
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; And try again
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dey
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bne :-
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sec
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rts
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; Acknowledge interrupt, is it necessary ???
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: lda #%00001000
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fixup26:sta ethack
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fixup28:sta ethack
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; Set packet address
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fixup27:lda etharr
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fixup28:sta ethpnr
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fixup29:lda etharr
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fixup30:sta ethpnr
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lda #$00
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ldx #%01000000 ; AUTO INCR.
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fixup29:sta ethptr
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fixup30:stx ethptr+1
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fixup31:sta ethptr
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fixup32:stx ethptr+1
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; Status written by CSMA
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lda #$00
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fixup31:sta ethdata
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fixup32:sta ethdata
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fixup33:sta ethdata
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fixup34:sta ethdata
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; Check packet length parity:
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; - Even packet length -> carry set -> add 6 bytes
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@ -352,10 +362,10 @@ fixup32:sta ethdata
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; The packet contains 3 extra words
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lda len
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adc #$05 ; Actually 5 or 6 depending on carry
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fixup33:sta ethdata
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fixup35:sta ethdata
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lda len+1
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adc #$00
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fixup34:sta ethdata
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fixup36:sta ethdata
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; Send the packet
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; ---------------
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@ -363,7 +373,7 @@ fixup34:sta ethdata
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; Write bytes from buffer
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jsr adjustptr
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: lda (ptr),y
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fixup35:sta ethdata
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fixup37:sta ethdata
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iny
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bne :-
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inc ptr+1
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@ -381,13 +391,14 @@ fixup35:sta ethdata
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; No
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: lda #$00
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fixup36:sta ethdata ; Fill byte
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fixup38:sta ethdata ; Fill byte
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:
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fixup37:sta ethdata ; Control byte
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fixup39:sta ethdata ; Control byte
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; Add packet to FIFO
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lda #%11000000 ; ENQUEUE PACKET - transmit packet
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fixup38:sta ethmmucr
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fixup40:sta ethmmucr
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clc
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rts
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;---------------------------------------------------------------------
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|
|
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|
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@ -48,10 +48,10 @@ bufaddr:.res 2 ; Address
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bufsize:.res 2 ; Size
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|
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; Jump table.
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.addr init
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.addr poll
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.addr send
|
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.addr exit
|
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jmp init
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jmp poll
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jmp send
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jmp exit
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;---------------------------------------------------------------------
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|
|
@ -96,7 +96,8 @@ fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
|
|||
.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
|
||||
.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
|
||||
.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
|
||||
.byte fixup26-fixup25
|
||||
.byte fixup26-fixup25, fixup27-fixup26, fixup28-fixup27
|
||||
.byte fixup29-fixup28, fixup30-fixup29
|
||||
|
||||
fixups = * - fixup
|
||||
|
||||
|
|
@ -144,23 +145,40 @@ init:
|
|||
inc ptr+1
|
||||
bcs :- ; Always
|
||||
|
||||
; Indirect Bus I/F mode, Address Auto-Increment
|
||||
:
|
||||
fixup01:lda mode
|
||||
ora #$03
|
||||
fixup02:sta mode
|
||||
|
||||
; Retry Time-value Register: = 2000 ?
|
||||
ldx #$00 ; Hibyte
|
||||
ldy #$17 ; Lobyte
|
||||
jsr set_addr
|
||||
lda #$07^$D0
|
||||
fixup03:eor data
|
||||
fixup04:eor data
|
||||
beq :+
|
||||
sec
|
||||
rts
|
||||
|
||||
; S/W Reset
|
||||
: lda #$80
|
||||
fixup01:sta mode
|
||||
fixup05:sta mode
|
||||
:
|
||||
fixup02:lda mode
|
||||
fixup06:lda mode
|
||||
bmi :-
|
||||
|
||||
; Indirect Bus I/F mode, Address Auto-Increment, Ping Block
|
||||
lda #$13
|
||||
fixup03:sta mode
|
||||
fixup07:sta mode
|
||||
|
||||
; Source Hardware Address Register: MAC Address
|
||||
ldx #$00 ; Hibyte
|
||||
ldy #$09 ; Lobyte
|
||||
jsr set_addr
|
||||
: lda mac,x
|
||||
fixup04:sta data
|
||||
fixup08:sta data
|
||||
inx
|
||||
cpx #$06
|
||||
bcc :-
|
||||
|
|
@ -171,17 +189,20 @@ fixup04:sta data
|
|||
ldy #$1A ; Lobyte
|
||||
jsr set_addr
|
||||
lda #$03
|
||||
fixup05:sta data
|
||||
fixup06:sta data
|
||||
fixup09:sta data
|
||||
fixup10:sta data
|
||||
|
||||
; Socket 0 Mode Register: MACRAW, MAC Filter
|
||||
; Socket 0 Command Register: OPEN
|
||||
ldy #$00
|
||||
jsr set_addrsocket0
|
||||
lda #$44
|
||||
fixup07:sta data
|
||||
fixup11:sta data
|
||||
lda #$01
|
||||
fixup08:sta data
|
||||
fixup12:sta data
|
||||
tya
|
||||
tax
|
||||
clc
|
||||
rts
|
||||
|
||||
;---------------------------------------------------------------------
|
||||
|
|
@ -190,19 +211,20 @@ poll:
|
|||
; Check for completion of previous command
|
||||
; Socket 0 Command Register: = 0 ?
|
||||
jsr set_addrcmdreg0
|
||||
fixup09:lda data
|
||||
fixup13:lda data
|
||||
beq :++
|
||||
|
||||
; No data available
|
||||
lda #$00
|
||||
: tax
|
||||
sec
|
||||
rts
|
||||
|
||||
; Socket 0 RX Received Size Register: != 0 ?
|
||||
: ldy #$26 ; Socket RX Received Size Register
|
||||
jsr set_addrsocket0
|
||||
fixup10:lda data ; Hibyte
|
||||
fixup11:ora data ; Lobyte
|
||||
fixup14:lda data ; Hibyte
|
||||
fixup15:ora data ; Lobyte
|
||||
beq :--
|
||||
|
||||
; Process the incoming data
|
||||
|
|
@ -268,17 +290,18 @@ common: jsr set_addrsocket0
|
|||
tax
|
||||
lda reg+1
|
||||
adc adv+1
|
||||
fixup12:sta data ; Hibyte
|
||||
fixup13:stx data ; Lobyte
|
||||
fixup16:sta data ; Hibyte
|
||||
fixup17:stx data ; Lobyte
|
||||
|
||||
; Set command register
|
||||
tya ; Restore command
|
||||
jsr set_addrcmdreg0
|
||||
fixup14:sta data
|
||||
fixup18:sta data
|
||||
|
||||
; Return data length (will be ignored for send)
|
||||
lda len
|
||||
ldx len+1
|
||||
clc
|
||||
rts
|
||||
|
||||
;---------------------------------------------------------------------
|
||||
|
|
@ -300,14 +323,14 @@ send:
|
|||
; Wait for completion of previous command
|
||||
; Socket 0 Command Register: = 0 ?
|
||||
: jsr set_addrcmdreg0
|
||||
fixup15:lda data
|
||||
fixup19:lda data
|
||||
bne :-
|
||||
|
||||
; Socket 0 TX Free Size Register: < length ?
|
||||
: ldy #$20 ; Socket TX Free Size Register
|
||||
jsr set_addrsocket0
|
||||
fixup16:lda data ; Hibyte
|
||||
fixup17:ldx data ; Lobyte
|
||||
fixup20:lda data ; Hibyte
|
||||
fixup21:ldx data ; Lobyte
|
||||
cpx len
|
||||
sbc len+1
|
||||
bcc :-
|
||||
|
|
@ -337,16 +360,16 @@ exit:
|
|||
;---------------------------------------------------------------------
|
||||
|
||||
set_addrphysical:
|
||||
fixup18:lda data ; Hibyte
|
||||
fixup19:ldy data ; Lobyte
|
||||
fixup22:lda data ; Hibyte
|
||||
fixup23:ldy data ; Lobyte
|
||||
sty reg
|
||||
sta reg+1
|
||||
and #>$1FFF ; Socket Mask Address (hibyte)
|
||||
ora bas ; Socket Base Address (hibyte)
|
||||
tax
|
||||
set_addr:
|
||||
fixup20:stx addr ; Hibyte
|
||||
fixup21:sty addr+1 ; Lobyte
|
||||
fixup24:stx addr ; Hibyte
|
||||
fixup25:sty addr+1 ; Lobyte
|
||||
rts
|
||||
|
||||
set_addrcmdreg0:
|
||||
|
|
@ -361,7 +384,7 @@ set_addrbase:
|
|||
beq set_addr ; Always
|
||||
|
||||
get_datacheckaddr:
|
||||
fixup22:lda data
|
||||
fixup26:lda data
|
||||
iny ; Physical address shadow (lobyte)
|
||||
bne :+
|
||||
inx ; Physical address shadow (hibyte)
|
||||
|
|
@ -402,10 +425,10 @@ mov_data:
|
|||
; R/W without address wraparound possible because
|
||||
; highest R/W address > actual R/W address ?
|
||||
; sec
|
||||
fixup23:sbc addr+1 ; Lobyte
|
||||
fixup27:sbc addr+1 ; Lobyte
|
||||
tay
|
||||
txa
|
||||
fixup24:sbc addr ; Hibyte
|
||||
fixup28:sbc addr ; Hibyte
|
||||
tax
|
||||
tya
|
||||
bcs :+
|
||||
|
|
@ -466,7 +489,7 @@ rw_data:eor #$FF ; Two's complement part 1
|
|||
|
||||
; Read data
|
||||
:
|
||||
fixup25:lda data
|
||||
fixup29:lda data
|
||||
sta (ptr),y
|
||||
iny
|
||||
bne :-
|
||||
|
|
@ -477,7 +500,7 @@ fixup25:lda data
|
|||
|
||||
; Write data
|
||||
: lda (ptr),y
|
||||
fixup26:sta data
|
||||
fixup30:sta data
|
||||
iny
|
||||
bne :-
|
||||
inc ptr+1
|
||||
|
|
|
|||
Loading…
Reference in a new issue