CC2538: added support for SSI1
This commit is contained in:
Ulf Knoblich
Ulf Knoblich
parent
60a301ef9f
commit
a388a1bcd7
6 changed files with 487 additions and 173 deletions
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@ -1,5 +1,9 @@
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/*
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* Copyright (c) 2013, University of Michigan.
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*
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* Copyright (c) 2015, Weptech elektronik GmbH
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* Author: Ulf Knoblich, ulf.knoblich@weptech.de
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -41,102 +45,281 @@
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#include "dev/spi.h"
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#include "dev/ssi.h"
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#include "dev/gpio.h"
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/*---------------------------------------------------------------------------*/
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/* Check port / pin settings for SPI0 and provide default values for spi_cfg */
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#ifndef SPI0_CLK_PORT
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#define SPI0_CLK_PORT (-1)
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#endif
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#ifndef SPI0_CLK_PIN
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#define SPI0_CLK_PIN (-1)
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#endif
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#if SPI0_CLK_PORT >= 0 && SPI0_CLK_PIN < 0 || \
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SPI0_CLK_PORT < 0 && SPI0_CLK_PIN >= 0
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#error Both SPI0_CLK_PORT and SPI0_CLK_PIN must be valid or invalid
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#endif
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#define SPI_CLK_PORT_BASE GPIO_PORT_TO_BASE(SPI_CLK_PORT)
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#define SPI_CLK_PIN_MASK GPIO_PIN_MASK(SPI_CLK_PIN)
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#define SPI_MOSI_PORT_BASE GPIO_PORT_TO_BASE(SPI_MOSI_PORT)
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#define SPI_MOSI_PIN_MASK GPIO_PIN_MASK(SPI_MOSI_PIN)
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#define SPI_MISO_PORT_BASE GPIO_PORT_TO_BASE(SPI_MISO_PORT)
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#define SPI_MISO_PIN_MASK GPIO_PIN_MASK(SPI_MISO_PIN)
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#ifndef SPI0_TX_PORT
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#define SPI0_TX_PORT (-1)
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#endif
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#ifndef SPI0_TX_PIN
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#define SPI0_TX_PIN (-1)
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#endif
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#if SPI0_TX_PORT >= 0 && SPI0_TX_PIN < 0 || \
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SPI0_TX_PORT < 0 && SPI0_TX_PIN >= 0
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#error Both SPI0_TX_PORT and SPI0_TX_PIN must be valid or invalid
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#endif
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/**
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* \brief Initialize the SPI bus.
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*
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* This SPI init() function uses the following defines to set the pins:
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* SPI_CLK_PORT SPI_CLK_PIN
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* SPI_MOSI_PORT SPI_MOSI_PIN
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* SPI_MISO_PORT SPI_MISO_PIN
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*
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* This sets the mode to Motorola SPI with the following format options:
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* Clock phase: 1; data captured on second (rising) edge
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* Clock polarity: 1; clock is high when idle
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* Data size: 8 bits
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*/
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#ifndef SPI0_RX_PORT
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#define SPI0_RX_PORT (-1)
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#endif
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#ifndef SPI0_RX_PIN
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#define SPI0_RX_PIN (-1)
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#endif
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#if SPI0_RX_PORT >= 0 && SPI0_RX_PIN < 0 || \
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SPI0_RX_PORT < 0 && SPI0_RX_PIN >= 0
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#error Both SPI0_RX_PORT and SPI0_RX_PIN must be valid or invalid
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#endif
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/* Here we check that either all or none of the ports are defined. As
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we did already check that both ports + pins are either defined or
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not for every pin, this means that we can check for an incomplete
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configuration by only looking at the port defines */
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/* If some SPI0 pads are valid */
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#if SPI0_CLK_PORT >= 0 || SPI0_TX_PORT >= 0 || SPI0_RX_PORT >= 0
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/* but not all */
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#if SPI0_CLK_PORT < 0 || SPI0_TX_PORT < 0 || SPI0_RX_PORT < 0
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#error Some SPI0 pad definitions are invalid
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#endif
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#define SPI0_PADS_VALID
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#endif
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/*---------------------------------------------------------------------------*/
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/* Check port / pin settings for SPI1 and provide default values for spi_cfg */
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#ifndef SPI1_CLK_PORT
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#define SPI1_CLK_PORT (-1)
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#endif
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#ifndef SPI1_CLK_PIN
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#define SPI1_CLK_PIN (-1)
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#endif
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#if SPI1_CLK_PORT >= 0 && SPI1_CLK_PIN < 0 || \
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SPI1_CLK_PORT < 0 && SPI1_CLK_PIN >= 0
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#error Both SPI1_CLK_PORT and SPI1_CLK_PIN must be valid or invalid
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#endif
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#ifndef SPI1_TX_PORT
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#define SPI1_TX_PORT (-1)
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#endif
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#ifndef SPI1_TX_PIN
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#define SPI1_TX_PIN (-1)
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#endif
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#if SPI1_TX_PORT >= 0 && SPI1_TX_PIN < 0 || \
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SPI1_TX_PORT < 0 && SPI1_TX_PIN >= 0
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#error Both SPI1_TX_PORT and SPI1_TX_PIN must be valid or invalid
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#endif
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#ifndef SPI1_RX_PORT
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#define SPI1_RX_PORT (-1)
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#endif
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#ifndef SPI1_RX_PIN
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#define SPI1_RX_PIN (-1)
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#endif
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#if SPI1_RX_PORT >= 0 && SPI1_RX_PIN < 0 || \
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SPI1_RX_PORT < 0 && SPI1_RX_PIN >= 0
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#error Both SPI1_RX_PORT and SPI1_RX_PIN must be valid or invalid
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#endif
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/* If some SPI1 pads are valid */
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#if SPI1_CLK_PORT >= 0 || SPI1_TX_PORT >= 0 || SPI1_RX_PORT >= 0
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/* but not all */
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#if SPI1_CLK_PORT < 0 || SPI1_TX_PORT < 0 || SPI1_RX_PORT < 0
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#error Some SPI1 pad definitions are invalid
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#endif
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#define SPI1_PADS_VALID
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#endif
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#ifdef SPI_DEFAULT_INSTANCE
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#if SPI_DEFAULT_INSTANCE == 0
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#ifndef SPI0_PADS_VALID
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#error SPI_DEFAULT_INSTANCE is set to SPI0, but its pads are not valid
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#endif
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#elif SPI_DEFAULT_INSTANCE == 1
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#ifndef SPI1_PADS_VALID
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#error SPI_DEFAULT_INSTANCE is set to SPI1, but its pads are not valid
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#endif
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#endif
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#endif
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#if (SPI0_CPRS_CPSDVSR & 1) == 1 || SPI0_CPRS_CPSDVSR < 2 || SPI0_CPRS_CPSDVSR > 254
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#error SPI0_CPRS_CPSDVSR must be an even number between 2 and 254
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#endif
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#if (SPI1_CPRS_CPSDVSR & 1) == 1 || SPI1_CPRS_CPSDVSR < 2 || SPI1_CPRS_CPSDVSR > 254
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#error SPI1_CPRS_CPSDVSR must be an even number between 2 and 254
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#endif
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/*---------------------------------------------------------------------------*/
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typedef struct {
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int8_t port;
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int8_t pin;
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} spi_pad_t;
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typedef struct {
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uint32_t base;
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uint32_t ioc_ssirxd_ssi;
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uint32_t ioc_pxx_sel_ssi_clkout;
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uint32_t ioc_pxx_sel_ssi_txd;
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uint8_t ssi_cprs_cpsdvsr;
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spi_pad_t clk;
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spi_pad_t tx;
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spi_pad_t rx;
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} spi_regs_t;
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/*---------------------------------------------------------------------------*/
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static const spi_regs_t spi_regs[SSI_INSTANCE_COUNT] = {
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{
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.base = SSI0_BASE,
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.ioc_ssirxd_ssi = IOC_SSIRXD_SSI0,
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.ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI0_CLKOUT,
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.ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI0_TXD,
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.ssi_cprs_cpsdvsr = SPI0_CPRS_CPSDVSR,
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.clk = { SPI0_CLK_PORT, SPI0_CLK_PIN },
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.tx = { SPI0_TX_PORT, SPI0_TX_PIN },
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.rx = { SPI0_RX_PORT, SPI0_RX_PIN }
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}, {
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.base = SSI1_BASE,
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.ioc_ssirxd_ssi = IOC_SSIRXD_SSI1,
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.ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI1_CLKOUT,
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.ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI1_TXD,
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.ssi_cprs_cpsdvsr = SPI1_CPRS_CPSDVSR,
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.clk = { SPI1_CLK_PORT, SPI1_CLK_PIN },
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.tx = { SPI1_TX_PORT, SPI1_TX_PIN },
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.rx = { SPI1_RX_PORT, SPI1_RX_PIN }
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}
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};
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/*---------------------------------------------------------------------------*/
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/* Deprecated function call provided for compatibility reasons */
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#ifdef SPI_DEFAULT_INSTANCE
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void
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spi_init(void)
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{
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spi_enable();
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spix_init(SPI_DEFAULT_INSTANCE);
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}
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#endif /* #ifdef SPI_DEFAULT_INSTANCE */
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/*---------------------------------------------------------------------------*/
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void
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spix_init(uint8_t spi)
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{
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const spi_regs_t *regs;
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if(spi >= SSI_INSTANCE_COUNT) {
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return;
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}
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regs = &spi_regs[spi];
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if(regs->clk.port < 0) {
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/* Port / pin configuration invalid. We checked for completeness
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above. If clk.port is < 0, this means that all other defines are
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< 0 as well */
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return;
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}
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spix_enable(spi);
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/* Start by disabling the peripheral before configuring it */
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REG(SSI0_BASE + SSI_CR1) = 0;
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REG(regs->base + SSI_CR1) = 0;
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/* Set the IO clock as the SSI clock */
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REG(SSI0_BASE + SSI_CC) = 1;
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REG(regs->base + SSI_CC) = 1;
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/* Set the mux correctly to connect the SSI pins to the correct GPIO pins */
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ioc_set_sel(SPI_CLK_PORT, SPI_CLK_PIN, IOC_PXX_SEL_SSI0_CLKOUT);
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ioc_set_sel(SPI_MOSI_PORT, SPI_MOSI_PIN, IOC_PXX_SEL_SSI0_TXD);
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REG(IOC_SSIRXD_SSI0) = (SPI_MISO_PORT * 8) + SPI_MISO_PIN;
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ioc_set_sel(regs->clk.port,
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regs->clk.pin,
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regs->ioc_pxx_sel_ssi_clkout);
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ioc_set_sel(regs->tx.port,
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regs->tx.pin,
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regs->ioc_pxx_sel_ssi_txd);
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REG(regs->ioc_ssirxd_ssi) = (regs->rx.port * 8) + regs->rx.pin;
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/* Put all the SSI gpios into peripheral mode */
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GPIO_PERIPHERAL_CONTROL(SPI_CLK_PORT_BASE, SPI_CLK_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(SPI_MOSI_PORT_BASE, SPI_MOSI_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(SPI_MISO_PORT_BASE, SPI_MISO_PIN_MASK);
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->clk.port),
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GPIO_PIN_MASK(regs->clk.pin));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->tx.port),
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GPIO_PIN_MASK(regs->tx.pin));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
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GPIO_PIN_MASK(regs->rx.pin));
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/* Disable any pull ups or the like */
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ioc_set_over(SPI_CLK_PORT, SPI_CLK_PIN, IOC_OVERRIDE_DIS);
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ioc_set_over(SPI_MOSI_PORT, SPI_MOSI_PIN, IOC_OVERRIDE_DIS);
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ioc_set_over(SPI_MISO_PORT, SPI_MISO_PIN, IOC_OVERRIDE_DIS);
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ioc_set_over(regs->clk.port, regs->clk.pin, IOC_OVERRIDE_DIS);
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ioc_set_over(regs->tx.port, regs->tx.pin, IOC_OVERRIDE_DIS);
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ioc_set_over(regs->rx.port, regs->rx.pin, IOC_OVERRIDE_DIS);
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/* Configure the clock */
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REG(SSI0_BASE + SSI_CPSR) = 2;
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REG(regs->base + SSI_CPSR) = regs->ssi_cprs_cpsdvsr;
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/* Configure the default SPI options.
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/*
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* Configure the default SPI options.
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* mode: Motorola frame format
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* clock: High when idle
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* data: Valid on rising edges of the clock
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* bits: 8 byte data
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*/
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REG(SSI0_BASE + SSI_CR0) = SSI_CR0_SPH | SSI_CR0_SPO | (0x07);
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REG(regs->base + SSI_CR0) = SSI_CR0_SPH | SSI_CR0_SPO | (0x07);
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/* Enable the SSI */
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REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE;
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REG(regs->base + SSI_CR1) |= SSI_CR1_SSE;
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_cs_init(uint8_t port, uint8_t pin)
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spix_enable(uint8_t spi)
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{
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GPIO_SOFTWARE_CONTROL(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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if(spi >= SSI_INSTANCE_COUNT) {
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return;
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}
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REG(SYS_CTRL_RCGCSSI) |= (1 << spi);
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}
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/*---------------------------------------------------------------------------*/
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void
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spix_disable(uint8_t spi)
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{
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if(spi >= SSI_INSTANCE_COUNT) {
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return;
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}
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REG(SYS_CTRL_RCGCSSI) &= ~(1 << spi);
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}
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/*---------------------------------------------------------------------------*/
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void
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spix_set_mode(uint8_t spi,
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uint32_t frame_format,
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uint32_t clock_polarity,
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uint32_t clock_phase,
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uint32_t data_size)
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{
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const spi_regs_t *regs;
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if(spi >= SSI_INSTANCE_COUNT) {
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return;
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}
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regs = &spi_regs[spi];
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/* Disable the SSI peripheral to configure it */
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REG(regs->base + SSI_CR1) = 0;
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/* Configure the SSI options */
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REG(regs->base + SSI_CR0) = clock_phase |
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clock_polarity |
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frame_format |
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(data_size - 1);
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/* Re-enable the SSI */
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REG(regs->base + SSI_CR1) |= SSI_CR1_SSE;
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}
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/*---------------------------------------------------------------------------*/
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void
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spix_cs_init(uint8_t port, uint8_t pin)
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{
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GPIO_SOFTWARE_CONTROL(GPIO_PORT_TO_BASE(port),
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GPIO_PIN_MASK(pin));
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ioc_set_over(port, pin, IOC_OVERRIDE_DIS);
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GPIO_SET_OUTPUT(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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GPIO_SET_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin));
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_enable(void)
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{
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/* Enable the clock for the SSI peripheral */
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REG(SYS_CTRL_RCGCSSI) |= 1;
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_disable(void)
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{
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/* Gate the clock for the SSI peripheral */
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REG(SYS_CTRL_RCGCSSI) &= ~1;
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}
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/*---------------------------------------------------------------------------*/
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void
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spi_set_mode(uint32_t frame_format, uint32_t clock_polarity,
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uint32_t clock_phase, uint32_t data_size)
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{
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/* Disable the SSI peripheral to configure it */
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REG(SSI0_BASE + SSI_CR1) = 0;
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/* Configure the SSI options */
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REG(SSI0_BASE + SSI_CR0) = clock_phase | clock_polarity | frame_format | (data_size - 1);
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/* Re-enable the SSI */
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REG(SSI0_BASE + SSI_CR1) |= SSI_CR1_SSE;
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}
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/** @} */
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