Merge pull request #1168 from bthebaudeau/enc28j60-fixes-and-improvements
enc28j60: Fixes and improvements
This commit is contained in:
Benoît Thébaudeau
commit
a2cae3359b
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@ -84,7 +84,6 @@
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#define MACONX_BANK 0x02
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#define MACON1 0x00
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#define MACON2 0x01
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#define MACON3 0x02
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#define MACON4 0x03
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#define MABBIPG 0x04
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@ -97,8 +96,6 @@
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#define MACON1_RXPAUS 0x04
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#define MACON1_MARXEN 0x01
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#define MACON2_MARST 0x80
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#define MACON3_PADCFG_FULL 0xe0
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#define MACON3_TXCRCEN 0x10
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#define MACON3_FRMLNEN 0x02
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@ -113,6 +110,8 @@
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#define MAADR4 0x03 /* MAADR<23:16> */
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#define MAADR5 0x00 /* MAADR<15:8> */
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#define MAADR6 0x01 /* MAADR<7:0> */
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#define MISTAT 0x0a
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#define EREVID 0x12
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#define EPKTCNT_BANK 0x01
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#define ERXFCON 0x18
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@ -128,10 +127,27 @@
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PROCESS(enc_watchdog_process, "Enc28j60 watchdog");
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static uint8_t initialized = 0;
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static uint8_t bank = ERXTX_BANK;
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static uint8_t enc_mac_addr[6];
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static int received_packets = 0;
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static int sent_packets = 0;
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/*---------------------------------------------------------------------------*/
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static uint8_t
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is_mac_mii_reg(uint8_t reg)
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{
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/* MAC or MII register (otherwise, ETH register)? */
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switch(bank) {
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case MACONX_BANK:
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return reg < EIE;
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case MAADRX_BANK:
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return reg <= MAADR2 || reg == MISTAT;
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case ERXTX_BANK:
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case EPKTCNT_BANK:
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default:
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return 0;
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}
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t
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readreg(uint8_t reg)
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@ -139,6 +155,10 @@ readreg(uint8_t reg)
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uint8_t r;
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enc28j60_arch_spi_select();
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enc28j60_arch_spi_write(0x00 | (reg & 0x1f));
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if(is_mac_mii_reg(reg)) {
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/* MAC and MII registers require that a dummy byte be read first. */
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enc28j60_arch_spi_read();
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}
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r = enc28j60_arch_spi_read();
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enc28j60_arch_spi_deselect();
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return r;
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@ -154,20 +174,37 @@ writereg(uint8_t reg, uint8_t data)
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}
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/*---------------------------------------------------------------------------*/
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static void
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setregbank(uint8_t bank)
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setregbitfield(uint8_t reg, uint8_t mask)
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{
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writereg(ECON1, (readreg(ECON1) & 0xfc) | (bank & 0x03));
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if(is_mac_mii_reg(reg)) {
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writereg(reg, readreg(reg) | mask);
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} else {
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enc28j60_arch_spi_select();
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enc28j60_arch_spi_write(0x80 | (reg & 0x1f));
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enc28j60_arch_spi_write(mask);
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enc28j60_arch_spi_deselect();
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}
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}
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/*---------------------------------------------------------------------------*/
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static void
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writedatabyte(uint8_t byte)
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clearregbitfield(uint8_t reg, uint8_t mask)
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{
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if(is_mac_mii_reg(reg)) {
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writereg(reg, readreg(reg) & ~mask);
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} else {
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enc28j60_arch_spi_select();
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/* The Write Buffer Memory (WBM) command is 0 1 1 1 1 0 1 0 */
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enc28j60_arch_spi_write(0x7a);
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enc28j60_arch_spi_write(byte);
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enc28j60_arch_spi_write(0xa0 | (reg & 0x1f));
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enc28j60_arch_spi_write(mask);
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enc28j60_arch_spi_deselect();
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}
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}
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/*---------------------------------------------------------------------------*/
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static void
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setregbank(uint8_t new_bank)
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{
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writereg(ECON1, (readreg(ECON1) & 0xfc) | (new_bank & 0x03));
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bank = new_bank;
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}
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/*---------------------------------------------------------------------------*/
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static void
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writedata(uint8_t *data, int datalen)
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@ -182,16 +219,10 @@ writedata(uint8_t *data, int datalen)
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enc28j60_arch_spi_deselect();
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t
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readdatabyte(void)
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static void
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writedatabyte(uint8_t byte)
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{
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uint8_t r;
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enc28j60_arch_spi_select();
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/* THe Read Buffer Memory (RBM) command is 0 0 1 1 1 0 1 0 */
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enc28j60_arch_spi_write(0x3a);
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r = enc28j60_arch_spi_read();
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enc28j60_arch_spi_deselect();
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return r;
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writedata(&byte, 1);
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}
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/*---------------------------------------------------------------------------*/
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static int
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@ -208,6 +239,14 @@ readdata(uint8_t *buf, int len)
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return i;
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t
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readdatabyte(void)
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{
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uint8_t r;
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readdata(&r, 1);
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return r;
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}
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/*---------------------------------------------------------------------------*/
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static void
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softreset(void)
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{
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@ -215,8 +254,27 @@ softreset(void)
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/* The System Command (soft reset) is 1 1 1 1 1 1 1 1 */
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enc28j60_arch_spi_write(0xff);
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enc28j60_arch_spi_deselect();
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bank = ERXTX_BANK;
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}
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/*---------------------------------------------------------------------------*/
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#if DEBUG
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static uint8_t
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readrev(void)
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{
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uint8_t rev;
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setregbank(MAADRX_BANK);
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rev = readreg(EREVID);
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switch(rev) {
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case 2:
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return 1;
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case 6:
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return 7;
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default:
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return rev;
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}
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}
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#endif
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/*---------------------------------------------------------------------------*/
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static void
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reset(void)
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{
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@ -282,11 +340,14 @@ reset(void)
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see Section 2.2 “Oscillator Start-up Timer.
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*/
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softreset();
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/* Workaround for erratum #2. */
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clock_delay_usec(1000);
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/* Wait for OST */
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while((readreg(ESTAT) & ESTAT_CLKRDY) == 0);
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softreset();
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setregbank(ERXTX_BANK);
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/* Set up receive buffer */
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writereg(ERXSTL, RX_BUF_START & 0xff);
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@ -295,16 +356,12 @@ reset(void)
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writereg(ERXNDH, RX_BUF_END >> 8);
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writereg(ERDPTL, RX_BUF_START & 0xff);
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writereg(ERDPTH, RX_BUF_START >> 8);
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writereg(ERXRDPTL, RX_BUF_START & 0xff);
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writereg(ERXRDPTH, RX_BUF_START >> 8);
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writereg(ERXRDPTL, RX_BUF_END & 0xff);
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writereg(ERXRDPTH, RX_BUF_END >> 8);
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/* Receive filters */
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setregbank(EPKTCNT_BANK);
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/* writereg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN |
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ERXFCON_MCEN | ERXFCON_BCEN);*/
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/* XXX: can't seem to get the unicast filter to work right now,
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using promiscous mode for now. */
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writereg(ERXFCON, 0);
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writereg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
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/*
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6.5 MAC Initialization Settings
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@ -313,13 +370,11 @@ reset(void)
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initialization. This only needs to be done once; the order of
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programming is unimportant.
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1. Clear the MARST bit in MACON2 to pull the MAC out of Reset.
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2. Set the MARXEN bit in MACON1 to enable the MAC to receive
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1. Set the MARXEN bit in MACON1 to enable the MAC to receive
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frames. If using full duplex, most applications should also set
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TXPAUS and RXPAUS to allow IEEE defined flow control to function.
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3. Configure the PADCFG, TXCRCEN and FULDPX bits of MACON3. Most
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2. Configure the PADCFG, TXCRCEN and FULDPX bits of MACON3. Most
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applications should enable automatic padding to at least 60 bytes
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and always append a valid CRC. For convenience, many applications
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may wish to set the FRMLNEN bit as well to enable frame length
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@ -327,48 +382,43 @@ reset(void)
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will be connected to a full-duplex configured remote node;
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otherwise, it should be left clear.
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4. Configure the bits in MACON4. Many applications may not need to
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modify the Reset default.
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3. Configure the bits in MACON4. For conformance to the IEEE 802.3
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standard, set the DEFER bit.
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5. Program the MAMXFL registers with the maximum frame length to
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4. Program the MAMXFL registers with the maximum frame length to
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be permitted to be received or transmitted. Normal network nodes
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are designed to handle packets that are 1518 bytes or less.
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6. Configure the Back-to-Back Inter-Packet Gap register,
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5. Configure the Back-to-Back Inter-Packet Gap register,
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MABBIPG. Most applications will program this register with 15h
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when Full-Duplex mode is used and 12h when Half-Duplex mode is
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used.
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7. Configure the Non-Back-to-Back Inter-Packet Gap register low
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6. Configure the Non-Back-to-Back Inter-Packet Gap register low
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byte, MAIPGL. Most applications will program this register with
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12h.
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8. If half duplex is used, the Non-Back-to-Back Inter-Packet Gap
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7. If half duplex is used, the Non-Back-to-Back Inter-Packet Gap
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register high byte, MAIPGH, should be programmed. Most
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applications will program this register to 0Ch.
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9. If Half-Duplex mode is used, program the Retransmission and
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8. If Half-Duplex mode is used, program the Retransmission and
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Collision Window registers, MACLCON1 and MACLCON2. Most
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applications will not need to change the default Reset values. If
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the network is spread over exceptionally long cables, the default
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value of MACLCON2 may need to be increased.
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10. Program the local MAC address into the
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MAADR0:MAADR5 registers.
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9. Program the local MAC address into the MAADR1:MAADR6 registers.
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*/
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setregbank(MACONX_BANK);
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/* Pull MAC out of reset */
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writereg(MACON2, 0);//readreg(MACON2) & (~MACON2_MARST));
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/* Turn on reception and IEEE-defined flow control */
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writereg(MACON1, readreg(MACON1) | (MACON1_MARXEN + MACON1_TXPAUS +
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MACON1_RXPAUS));
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setregbitfield(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
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/* Set padding, crc, full duplex */
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writereg(MACON3, readreg(MACON3) | (MACON3_PADCFG_FULL + MACON3_TXCRCEN +
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MACON3_FULDPX + MACON3_FRMLNEN));
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setregbitfield(MACON3, MACON3_PADCFG_FULL | MACON3_TXCRCEN | MACON3_FULDPX |
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MACON3_FRMLNEN);
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/* Don't modify MACON4 */
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@ -381,7 +431,6 @@ reset(void)
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/* Set non-back-to-back packet gap */
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writereg(MAIPGL, 0x12);
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writereg(MAIPGH, 0x0c);
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/* Set MAC address */
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setregbank(MAADRX_BANK);
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@ -392,10 +441,6 @@ reset(void)
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writereg(MAADR2, enc_mac_addr[1]);
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writereg(MAADR1, enc_mac_addr[0]);
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/* Receive filters */
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setregbank(EPKTCNT_BANK);
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writereg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
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/*
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6.6 PHY Initialization Settings
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@ -425,7 +470,7 @@ reset(void)
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/* Don't worry about PHY configuration for now */
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/* Turn on autoincrement for buffer access */
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writereg(ECON2, readreg(ECON2) | ECON2_AUTOINC);
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setregbitfield(ECON2, ECON2_AUTOINC);
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/* Turn on reception */
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writereg(ECON1, ECON1_RXEN);
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@ -445,13 +490,15 @@ enc28j60_init(uint8_t *mac_addr)
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reset();
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PRINTF("ENC28J60 rev. B%d\n", readrev());
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initialized = 1;
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}
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/*---------------------------------------------------------------------------*/
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int
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enc28j60_send(uint8_t *data, uint16_t datalen)
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{
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int padding = 0;
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uint16_t dataend;
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if(!initialized) {
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return -1;
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@ -488,49 +535,46 @@ enc28j60_send(uint8_t *data, uint16_t datalen)
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/* Write the transmission control register as the first byte of the
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output packet. We write 0x00 to indicate that the default
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configuration (the values in MACON3) will be used. */
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#define WITH_MANUAL_PADDING 1
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#if WITH_MANUAL_PADDING
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#define PADDING_MIN_SIZE 60
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writedatabyte(0x0B); /* POVERRIDE, PCRCEN, PHUGEEN. Not PPADEN */
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if(datalen < PADDING_MIN_SIZE) {
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padding = PADDING_MIN_SIZE - datalen;
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} else {
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padding = 0;
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}
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#else /* WITH_MANUAL_PADDING */
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writedatabyte(0x00); /* MACON3 */
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padding = 0;
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#endif /* WITH_MANUAL_PADDING */
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/* Write a pointer to the last data byte. */
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writereg(ETXNDL, (TX_BUF_START + datalen + 0 + padding) & 0xff);
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writereg(ETXNDH, (TX_BUF_START + datalen + 0 + padding) >> 8);
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writedata(data, datalen);
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if(padding > 0) {
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uint8_t padding_buf[60];
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memset(padding_buf, 0, padding);
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writedata(padding_buf, padding);
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}
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/* Write a pointer to the last data byte. */
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dataend = TX_BUF_START + datalen;
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writereg(ETXNDL, dataend & 0xff);
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writereg(ETXNDH, dataend >> 8);
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/* Clear EIR.TXIF */
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writereg(EIR, readreg(EIR) & (~EIR_TXIF));
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clearregbitfield(EIR, EIR_TXIF);
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/* Don't care about interrupts for now */
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/* Send the packet */
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writereg(ECON1, readreg(ECON1) | ECON1_TXRTS);
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setregbitfield(ECON1, ECON1_TXRTS);
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while((readreg(ECON1) & ECON1_TXRTS) > 0);
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#if DEBUG
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if((readreg(ESTAT) & ESTAT_TXABRT) != 0) {
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PRINTF("enc28j60: tx err: %d: %02x:%02x:%02x:%02x:%02x:%02x\n", datalen,
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uint16_t erdpt;
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uint8_t tsv[7];
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erdpt = (readreg(ERDPTH) << 8) | readreg(ERDPTL);
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writereg(ERDPTL, (dataend + 1) & 0xff);
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writereg(ERDPTH, (dataend + 1) >> 8);
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readdata(tsv, sizeof(tsv));
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writereg(ERDPTL, erdpt & 0xff);
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writereg(ERDPTH, erdpt >> 8);
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PRINTF("enc28j60: tx err: %d: %02x:%02x:%02x:%02x:%02x:%02x\n"
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" tsv: %02x%02x%02x%02x%02x%02x%02x\n", datalen,
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0xff & data[0], 0xff & data[1], 0xff & data[2],
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0xff & data[3], 0xff & data[4], 0xff & data[5]);
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0xff & data[3], 0xff & data[4], 0xff & data[5],
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tsv[6], tsv[5], tsv[4], tsv[3], tsv[2], tsv[1], tsv[0]);
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} else {
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PRINTF("enc28j60: tx: %d: %02x:%02x:%02x:%02x:%02x:%02x\n", datalen,
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0xff & data[0], 0xff & data[1], 0xff & data[2],
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0xff & data[3], 0xff & data[4], 0xff & data[5]);
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}
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#endif
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sent_packets++;
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PRINTF("enc28j60: sent_packets %d\n", sent_packets);
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return datalen;
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@ -545,6 +589,10 @@ enc28j60_read(uint8_t *buffer, uint16_t bufsize)
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uint8_t status[2];
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uint8_t length[2];
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if(!initialized) {
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return -1;
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}
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err = 0;
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setregbank(EPKTCNT_BANK);
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@ -604,7 +652,7 @@ enc28j60_read(uint8_t *buffer, uint16_t bufsize)
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writereg(ERXRDPTL, next & 0xff);
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writereg(ERXRDPTH, next >> 8);
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writereg(ECON2, readreg(ECON2) | ECON2_PKTDEC);
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setregbitfield(ECON2, ECON2_PKTDEC);
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if(err) {
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PRINTF("enc28j60: rx err: flushed %d\n", len);
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