Merge pull request #777 from atiselsts/msp430f5xxx_timing_fixes

Fix time accounting on msp430 Series 5 MCU based platforms
This commit is contained in:
Nicolas Tsiftes 2014-08-30 22:28:45 +02:00
commit 97037763ad
2 changed files with 36 additions and 8 deletions

View file

@ -41,12 +41,26 @@
#define MAX_TICKS (~((clock_time_t)0) / 2)
#define CLOCK_LT(a, b) ((int16_t)((a)-(b)) < 0)
static volatile unsigned long seconds;
static volatile clock_time_t count = 0;
/* last_tar is used for calculating clock_fine, last_ccr might be better? */
static volatile uint16_t last_tar = 0;
/*---------------------------------------------------------------------------*/
static inline uint16_t
read_tar(void)
{
/* Same as clock_counter(), but can be inlined */
uint16_t t1, t2;
do {
t1 = TA1R;
t2 = TA1R;
} while(t1 != t2);
return t1;
}
/*---------------------------------------------------------------------------*/
ISR(TIMER1_A1, timera1)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
@ -59,8 +73,9 @@ ISR(TIMER1_A1, timera1)
* Occurs when timer state is toggled between STOP and CONT. */
while(TA1CTL & MC1 && TA1CCR1 - TA1R == 1);
last_tar = read_tar();
/* Make sure interrupt time is future */
do {
while(!CLOCK_LT(last_tar, TA1CCR1)) {
TA1CCR1 += INTERVAL;
++count;
@ -76,9 +91,8 @@ ISR(TIMER1_A1, timera1)
++seconds;
energest_flush();
}
} while((TA1CCR1 - TA1R) > INTERVAL);
last_tar = TA1R;
last_tar = read_tar();
}
if(etimer_pending() &&
(etimer_next_expiration_time() - count - 1) > MAX_TICKS) {

View file

@ -43,12 +43,26 @@
#define MAX_TICKS (~((clock_time_t)0) / 2)
#define CLOCK_LT(a, b) ((int16_t)((a)-(b)) < 0)
static volatile unsigned long seconds;
static volatile clock_time_t count = 0;
/* last_tar is used for calculating clock_fine, last_ccr might be better? */
static unsigned short last_tar = 0;
/*---------------------------------------------------------------------------*/
static inline uint16_t
read_tar(void)
{
/* Same as clock_counter(), but can be inlined */
uint16_t t1, t2;
do {
t1 = TA1R;
t2 = TA1R;
} while(t1 != t2);
return t1;
}
/*---------------------------------------------------------------------------*/
ISR(TIMER1_A1, timera1)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
@ -59,8 +73,9 @@ ISR(TIMER1_A1, timera1)
* Occurrs when timer state is toggled between STOP and CONT. */
while(TA1CTL & MC1 && TA1CCR1 - TA1R == 1);
last_tar = read_tar();
/* Make sure interrupt time is future */
do {
while(!CLOCK_LT(last_tar, TA1CCR1)) {
/* TACTL &= ~MC1;*/
TA1CCR1 += INTERVAL;
/* TACTL |= MC1;*/
@ -78,9 +93,8 @@ ISR(TIMER1_A1, timera1)
++seconds;
energest_flush();
}
} while((TA1CCR1 - TA1R) > INTERVAL);
last_tar = TA1R;
last_tar = read_tar();
}
if(etimer_pending() &&
(etimer_next_expiration_time() - count - 1) > MAX_TICKS) {