Merge pull request #777 from atiselsts/msp430f5xxx_timing_fixes
Fix time accounting on msp430 Series 5 MCU based platforms
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commit
97037763ad
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@ -41,12 +41,26 @@
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#define MAX_TICKS (~((clock_time_t)0) / 2)
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#define CLOCK_LT(a, b) ((int16_t)((a)-(b)) < 0)
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static volatile unsigned long seconds;
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static volatile clock_time_t count = 0;
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/* last_tar is used for calculating clock_fine, last_ccr might be better? */
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static volatile uint16_t last_tar = 0;
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/*---------------------------------------------------------------------------*/
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static inline uint16_t
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read_tar(void)
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{
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/* Same as clock_counter(), but can be inlined */
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uint16_t t1, t2;
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do {
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t1 = TA1R;
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t2 = TA1R;
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} while(t1 != t2);
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return t1;
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}
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/*---------------------------------------------------------------------------*/
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ISR(TIMER1_A1, timera1)
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{
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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@ -59,8 +73,9 @@ ISR(TIMER1_A1, timera1)
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* Occurs when timer state is toggled between STOP and CONT. */
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while(TA1CTL & MC1 && TA1CCR1 - TA1R == 1);
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last_tar = read_tar();
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/* Make sure interrupt time is future */
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do {
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while(!CLOCK_LT(last_tar, TA1CCR1)) {
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TA1CCR1 += INTERVAL;
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++count;
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@ -76,9 +91,8 @@ ISR(TIMER1_A1, timera1)
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++seconds;
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energest_flush();
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}
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} while((TA1CCR1 - TA1R) > INTERVAL);
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last_tar = TA1R;
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last_tar = read_tar();
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}
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if(etimer_pending() &&
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(etimer_next_expiration_time() - count - 1) > MAX_TICKS) {
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@ -43,12 +43,26 @@
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#define MAX_TICKS (~((clock_time_t)0) / 2)
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#define CLOCK_LT(a, b) ((int16_t)((a)-(b)) < 0)
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static volatile unsigned long seconds;
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static volatile clock_time_t count = 0;
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/* last_tar is used for calculating clock_fine, last_ccr might be better? */
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static unsigned short last_tar = 0;
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/*---------------------------------------------------------------------------*/
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static inline uint16_t
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read_tar(void)
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{
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/* Same as clock_counter(), but can be inlined */
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uint16_t t1, t2;
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do {
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t1 = TA1R;
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t2 = TA1R;
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} while(t1 != t2);
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return t1;
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}
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/*---------------------------------------------------------------------------*/
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ISR(TIMER1_A1, timera1)
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{
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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@ -59,8 +73,9 @@ ISR(TIMER1_A1, timera1)
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* Occurrs when timer state is toggled between STOP and CONT. */
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while(TA1CTL & MC1 && TA1CCR1 - TA1R == 1);
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last_tar = read_tar();
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/* Make sure interrupt time is future */
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do {
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while(!CLOCK_LT(last_tar, TA1CCR1)) {
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/* TACTL &= ~MC1;*/
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TA1CCR1 += INTERVAL;
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/* TACTL |= MC1;*/
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@ -78,9 +93,8 @@ ISR(TIMER1_A1, timera1)
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++seconds;
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energest_flush();
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}
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} while((TA1CCR1 - TA1R) > INTERVAL);
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last_tar = TA1R;
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last_tar = read_tar();
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}
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if(etimer_pending() &&
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(etimer_next_expiration_time() - count - 1) > MAX_TICKS) {
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