From 9195b49c180787b0e6b7f76b9952c8a68255ff44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Sat, 23 Jul 2016 23:43:34 +0200 Subject: [PATCH] ARM: CMSIS-CORE: Introduce NVIC_IsIRQEnabled() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This function returns the enable state of an interrupt. Signed-off-by: Benoît Thébaudeau --- cpu/arm/common/CMSIS/core_cm0.h | 13 +++++++++++++ cpu/arm/common/CMSIS/core_cm0plus.h | 13 +++++++++++++ cpu/arm/common/CMSIS/core_cm3.h | 13 +++++++++++++ cpu/arm/common/CMSIS/core_cm4.h | 13 +++++++++++++ cpu/arm/common/CMSIS/core_cm7.h | 13 +++++++++++++ 5 files changed, 65 insertions(+) diff --git a/cpu/arm/common/CMSIS/core_cm0.h b/cpu/arm/common/CMSIS/core_cm0.h index 711dad551..1ce683576 100644 --- a/cpu/arm/common/CMSIS/core_cm0.h +++ b/cpu/arm/common/CMSIS/core_cm0.h @@ -621,6 +621,19 @@ typedef struct #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +/** + \brief Get External Interrupt Enable State + \details Returns whether a device-specific interrupt is enabled in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + \return 0 Interrupt is disabled. + \return 1 Interrupt is enabled. + */ +__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. diff --git a/cpu/arm/common/CMSIS/core_cm0plus.h b/cpu/arm/common/CMSIS/core_cm0plus.h index b04aa3905..8dc698a9a 100644 --- a/cpu/arm/common/CMSIS/core_cm0plus.h +++ b/cpu/arm/common/CMSIS/core_cm0plus.h @@ -737,6 +737,19 @@ typedef struct #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +/** + \brief Get External Interrupt Enable State + \details Returns whether a device-specific interrupt is enabled in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + \return 0 Interrupt is disabled. + \return 1 Interrupt is enabled. + */ +__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. diff --git a/cpu/arm/common/CMSIS/core_cm3.h b/cpu/arm/common/CMSIS/core_cm3.h index b4ac4c7b0..de1113688 100644 --- a/cpu/arm/common/CMSIS/core_cm3.h +++ b/cpu/arm/common/CMSIS/core_cm3.h @@ -1444,6 +1444,19 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) } +/** + \brief Get External Interrupt Enable State + \details Returns whether a device-specific interrupt is enabled in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + \return 0 Interrupt is disabled. + \return 1 Interrupt is enabled. + */ +__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. diff --git a/cpu/arm/common/CMSIS/core_cm4.h b/cpu/arm/common/CMSIS/core_cm4.h index dc840ebf2..218bc0dfa 100644 --- a/cpu/arm/common/CMSIS/core_cm4.h +++ b/cpu/arm/common/CMSIS/core_cm4.h @@ -1618,6 +1618,19 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) } +/** + \brief Get External Interrupt Enable State + \details Returns whether a device-specific interrupt is enabled in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + \return 0 Interrupt is disabled. + \return 1 Interrupt is enabled. + */ +__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller. diff --git a/cpu/arm/common/CMSIS/core_cm7.h b/cpu/arm/common/CMSIS/core_cm7.h index 3b7530ad5..1c1a5e68f 100644 --- a/cpu/arm/common/CMSIS/core_cm7.h +++ b/cpu/arm/common/CMSIS/core_cm7.h @@ -1826,6 +1826,19 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) } +/** + \brief Get External Interrupt Enable State + \details Returns whether a device-specific interrupt is enabled in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + \return 0 Interrupt is disabled. + \return 1 Interrupt is enabled. + */ +__STATIC_INLINE uint32_t NVIC_IsIRQEnabled(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + /** \brief Enable External Interrupt \details Enables a device-specific interrupt in the NVIC interrupt controller.