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IRIS port is working with uIPv6

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This commit is contained in:
HATATANI Shinta 2011-06-15 17:18:20 +09:00
parent cae1e122e8
commit 8f30113c50
11 changed files with 85 additions and 338 deletions
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22
cpu/avr/radio/rf230/hal.h
View file

@ -75,10 +75,12 @@
// RAVENUSB_C : used for USB key or Raven card
// RCB_B : RZ200 kit from Atmel based on 1281V
// ZIGBIT : Zigbit module from Meshnetics
// IRIS : IRIS Mote from MEMSIC
#define RAVEN_D 4
#define RAVENUSB_C 1
#define RCB_B 2
#define ZIGBIT 3
#define IRIS 5
@ -168,6 +170,26 @@
# define HAS_CW_MODE
# define HAS_SPARE_TIMER
#elif HARWARE_REVISION == IRIS
/* 1281 IRIS */
# define SSPORT B
# define SSPIN (0x00)
# define SPIPORT B
# define MOSIPIN (0x02)
# define MISOPIN (0x03)
# define SCKPIN (0x01)
# define RSTPORT A
# define RSTPIN (0x06)
# define IRQPORT D
# define IRQPIN (0x04)
# define SLPTRPORT B
# define SLPTRPIN (0x07)
//# define TXCWPORT B
//# define TXCWPIN (0x07)
# define USART 1
# define USARTVECT USART1_RX_vect
//# define TICKTIMER 3
//# define HAS_SPARE_TIMER // Not used
#else
#error "Platform undefined in hal.h"

22
cpu/avr/radio/rf230bb/hal.h
View file

@ -74,11 +74,13 @@
// RCB_B : RZ200 kit from Atmel based on 1281V
// ZIGBIT : Zigbit module from Meshnetics
// ATMEGA128RFA1 : Bare chip with internal radio
// IRIS : IRIS Mote from MEMSIC
#define RAVEN_D 4
#define RAVENUSB_C 1
#define RCB_B 2
#define ZIGBIT 3
#define ATMEGA128RFA1 4
#define IRIS 5
@ -214,6 +216,26 @@
# define HAS_SPARE_TIMER
#elif HARWARE_REVISION == IRIS
/* 1281 IRIS */
# define SSPORT B
# define SSPIN (0x00)
# define SPIPORT B
# define MOSIPIN (0x02)
# define MISOPIN (0x03)
# define SCKPIN (0x01)
# define RSTPORT A
# define RSTPIN (0x06)
# define IRQPORT D
# define IRQPIN (0x04)
# define SLPTRPORT B
# define SLPTRPIN (0x07)
//# define TXCWPORT B
//# define TXCWPIN (0x07)
# define USART 1
# define USARTVECT USART1_RX_vect
//# define TICKTIMER 3
//# define HAS_SPARE_TIMER // Not used
#else
#error "Platform undefined in hal.h"

26
platform/iris/Makefile.micaz → platform/iris/Makefile.iris
View file

@ -1,12 +1,12 @@
CONTIKI_TARGET_DIRS = . dev dev/sensors
CONTIKI_CORE=contiki-micaz
CONTIKI_CORE=contiki-iris
CONTIKI_TARGET_MAIN = ${CONTIKI_CORE}.o
SENSOR_BOARD_SOURCEFILES = mts300.c
CONTIKI_TARGET_SOURCEFILES += adc.c rs232.c cfs-eeprom.c contiki-micaz-main.c \
leds-arch.c cc2420.c init-net.c node-id.c \
clock.c spi.c cc2420-arch.c rtimer-arch.c ds2401.c \
CONTIKI_TARGET_SOURCEFILES += adc.c rs232.c cfs-eeprom.c contiki-iris-main.c \
leds-arch.c init-net.c node-id.c \
clock.c spi.c rtimer-arch.c ds2401.c \
battery-sensor.c slip.c slip_uart0.c
CONTIKI_TARGET_SOURCEFILES += $(SENSOR_BOARD_SOURCEFILES)
@ -14,10 +14,15 @@ CONTIKI_TARGET_SOURCEFILES += $(SENSOR_BOARD_SOURCEFILES)
CONTIKIAVR=$(CONTIKI)/cpu/avr
CONTIKIBOARD=.
# MicaZ runs on Clock rate 7.3728 MHz
CONTIKI_PLAT_DEFS = -DF_CPU=7372800UL -DAUTO_CRC_PADDING=2
# IRIS runs on Clock rate 8 MHz
CONTIKI_PLAT_DEFS = -DF_CPU=8000000UL -DAUTO_CRC_PADDING=2 #-DUSART_BAUD_115200
MCU=atmega128
MCU=atmega1281
AVRDUDE_OPTIONS=-V
AVRDUDE_PROGRAMMER=mib510
#AVRDUDE_PROGRAMMER=jtag2
#AVRDUDE_PORT=usb
AVRDUDE_PORT=$(PORT)
include $(CONTIKIAVR)/Makefile.avr
@ -40,7 +45,7 @@ endif
ifeq ($(PORT), )
ifndef WINDIR
PORT = /dev/ttyS0
PORT = /dev/ttyUSB0
else
PORT = COM1
endif
@ -53,3 +58,8 @@ ifneq ($(strip $(HAVE_PRGBOARD_FILE)), )
include $(PRGBOARD_FILE)
endif
include $(CONTIKIAVR)/radio/Makefile.radio
ifdef UIP_CONF_IPV6
CFLAGS += -DWITH_UIP6=1
endif

5
platform/iris/buildscripts/Makefile.mib510
View file

@ -1,5 +0,0 @@
%.upload: %.srec
uisp -dprog=mib510 -dserial=$(PORT) -dpart=ATmega128 --wr_fuse_h=0xd1 --wr_fuse_e=ff --erase --upload if=$< --verify
erase:
uisp -dprog=mib510 -dserial=$(PORT) -dpart=ATmega128 --wr_fuse_h=0xd9 --wr_fuse_e=ff --erase

10
platform/iris/contiki-conf.h
View file

@ -55,7 +55,7 @@
#define NETSTACK_CONF_RDC nullrdc_driver
#define NETSTACK_CONF_FRAMER framer_802154
#define CC2420_CONF_AUTOACK 1
#define RF230_CONF_AUTOACK 1
#define MAC_CONF_CHANNEL_CHECK_RATE 8
#define RIME_CONF_NO_POLITE_ANNOUCEMENTS 0
#define CXMAC_CONF_ANNOUNCEMENTS 0
@ -69,7 +69,7 @@
#define NETSTACK_CONF_RDC cxmac_driver
#define NETSTACK_CONF_FRAMER framer_802154
#define CC2420_CONF_AUTOACK 1
#define RF230_CONF_AUTOACK 1
#define MAC_CONF_CHANNEL_CHECK_RATE 8
#define COLLECT_CONF_ANNOUNCEMENTS 1
@ -158,8 +158,8 @@
#endif
#define TIMESYNCH_CONF_ENABLED 1
#define CC2420_CONF_TIMESTAMPS 1
#define CC2420_CONF_SYMBOL_LOOP_COUNT 500
#define RF230_CONF_TIMESTAMPS 0
#define RF230_CONF_SYMBOL_LOOP_COUNT 500
#define WITH_NULLMAC 0
@ -167,7 +167,7 @@
#define CLIF
/* The process names are not used to save RAM */
#define PROCESS_CONF_NO_PROCESS_NAMES 1
#define PROCESS_CONF_NO_PROCESS_NAMES 0
#define UIP_CONF_ICMP_DEST_UNREACH 1

1
platform/iris/contiki-micaz-main.c → platform/iris/contiki-iris-main.c
View file

@ -113,6 +113,7 @@ main(void)
/* Autostart processes */
autostart_start(autostart_processes);
mmem_init();
/* Main scheduler loop */
do {

69
platform/iris/dev/cc2420-arch.c
View file

@ -1,69 +0,0 @@
/*
* Copyright (c) 2009, University of Colombo School of Computing
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the Contiki operating system.
*
* @(#)$$
*/
#include <avr/io.h>
#include "contiki.h"
#include "contiki-net.h"
#include "dev/spi.h"
#include "dev/cc2420.h"
#include "dev/leds.h"
void
cc2420_arch_init(void)
{
SFIOR |= BV(PUD); /* Beware, disable all pull-ups. */
spi_init();
DDRA |= BV(CC2420_RESET_PIN);
DDRA |= BV(CC2420_VREG_PIN);
DDRB &= ~BV(CC2420_FIFO_PIN);
DDRD &= ~BV(CC2420_CCA_PIN);
DDRD &= ~BV(CC2420_SFD_PIN);
DDRE &= ~BV(CC2420_FIFOP_PIN);
PORTA |= BV(CC2420_RESET_PIN);
PORTB |= BV(CC2420_CSN_PIN);
CC2420_SPI_DISABLE(); /* Unselect radio. */
}
ISR(CC2420_IRQ_VECTOR)
{
/* TODO : wakeup from sleep mode */
cc2420_interrupt();
}

160
platform/iris/dev/clock.c
View file

@ -1,160 +0,0 @@
/*
* Copyright (c) 2009, University of Colombo School of Computing
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the Contiki operating system.
*
* @(#)$$
*/
#include "sys/clock.h"
#include "sys/etimer.h"
#include <avr/io.h>
#include <avr/interrupt.h>
static volatile clock_time_t count, scount;
static volatile unsigned long seconds;
/*---------------------------------------------------------------------------*/
ISR(TIMER0_COMP_vect)
{
count++;
if(++scount == CLOCK_SECOND) {
scount = 0;
seconds++;
}
if(etimer_pending()) {
etimer_request_poll();
}
}
/*---------------------------------------------------------------------------*/
void
clock_init(void)
{
/* Disable interrupts*/
cli();
/* Disable compare match interrupts and overflow interrupts. */
TIMSK &= ~( _BV(TOIE0) | _BV(OCIE0) );
/**
* set Timer/Counter0 to be asynchronous
* from the CPU clock with a second external
* clock(32,768kHz) driving it.
*/
ASSR |= _BV(AS0);
/*
* Set timer control register:
* - prescale: 32 (CS00 and CS01)
* - counter reset via comparison register (WGM01)
*/
TCCR0 = _BV(CS00) | _BV(CS01) | _BV(WGM01);
/* Set counter to zero */
TCNT0 = 0;
/*
* 128 clock ticks per second.
* 32,768 = 32 * 8 * 128
*/
OCR0 = 8;
/* Clear interrupt flag register */
TIFR = 0x00;
/**
* Wait for TCN0UB, OCR0UB, and TCR0UB.
*
*/
while(ASSR & 0x07);
/* Raise interrupt when value in OCR0 is reached. */
TIMSK |= _BV(OCIE0);
count = 0;
/* enable all interrupts*/
sei();
}
/*---------------------------------------------------------------------------*/
clock_time_t
clock_time(void)
{
clock_time_t tmp;
do {
tmp = count;
} while(tmp != count);
return tmp;
}
/*---------------------------------------------------------------------------*/
/**
* Delay the CPU for a multiple of TODO
*/
void
clock_delay(unsigned int i)
{
for (; i > 0; i--) { /* Needs fixing XXX */
unsigned j;
for (j = 50; j > 0; j--)
asm volatile("nop");
}
}
/*---------------------------------------------------------------------------*/
/**
* Wait for a multiple of 1 / 128 sec = 7.8125 ms.
*
*/
void
clock_wait(int i)
{
clock_time_t start;
start = clock_time();
while(clock_time() - start < (clock_time_t)i);
}
/*---------------------------------------------------------------------------*/
void
clock_set_seconds(unsigned long sec)
{
// TODO
}
/*---------------------------------------------------------------------------*/
unsigned long
clock_seconds(void)
{
unsigned long tmp;
do {
tmp = seconds;
} while(tmp != seconds);
return tmp;
}
/*---------------------------------------------------------------------------*/

8
platform/iris/init-net.c
View file

@ -43,7 +43,7 @@
#include <avr/pgmspace.h>
#include "contiki.h"
#include "dev/cc2420.h"
#include "rf230bb.h"
#include "dev/rs232.h"
#include "dev/slip.h"
#include "dev/leds.h"
@ -124,7 +124,7 @@ init_net(void)
{
set_rime_addr();
cc2420_init();
rf230_init();
{
uint8_t longaddr[8];
uint16_t shortaddr;
@ -137,9 +137,9 @@ init_net(void)
longaddr[0], longaddr[1], longaddr[2], longaddr[3],
longaddr[4], longaddr[5], longaddr[6], longaddr[7]);
cc2420_set_pan_addr(IEEE802154_PANID, shortaddr, longaddr);
rf230_set_pan_addr(IEEE802154_PANID, shortaddr, longaddr);
}
cc2420_set_channel(RF_CHANNEL);
rf230_set_channel(RF_CHANNEL);
#if WITH_UIP6

84
platform/iris/platform-conf.h
View file

@ -46,11 +46,14 @@
*/
#define PLATFORM PLATFORM_AVR
#define HARWARE_REVISION IRIS
//#define RAVEN_REVISION RAVEN_D
/*
* MCU and clock rate.
* MICAZ runs on 7.3728 MHz clock.
*/
#define MCU_MHZ 7
#define MCU_MHZ 8
/* Clock ticks per second */
#define CLOCK_CONF_SECOND 128
@ -77,7 +80,7 @@
#define EEPROM_NODE_ID_START 0x00
#define NETSTACK_CONF_RADIO cc2420_driver
#define NETSTACK_CONF_RADIO rf230_driver
/*
@ -113,83 +116,6 @@
#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
/*
* SPI bus - CC2420 pin configuration.
*/
#define CC2420_CONF_SYMBOL_LOOP_COUNT 500
/*
* SPI bus - CC2420 pin configuration.
*/
#define FIFO_P 6
#define FIFO 7
#define CCA 6
#define SFD 4
#define CSN 0
#define VREG_EN 5
#define RESET_N 6
/* - Input: FIFOP from CC2420 - ATMEGA128 PORTE, PIN6 */
#define CC2420_FIFOP_PORT(type) P##type##E
#define CC2420_FIFOP_PIN 6
/* - Input: FIFO from CC2420 - ATMEGA128 PORTB, PIN7 */
#define CC2420_FIFO_PORT(type) P##type##B
#define CC2420_FIFO_PIN 7
/* - Input: CCA from CC2420 - ATMEGA128 PORTD, PIN6 */
#define CC2420_CCA_PORT(type) P##type##D
#define CC2420_CCA_PIN 6
/* - Input: SFD from CC2420 - ATMEGA128 PORTD, PIN4 */
#define CC2420_SFD_PORT(type) P##type##D
#define CC2420_SFD_PIN 4
/* - Output: SPI Chip Select (CS_N) - ATMEGA128 PORTB, PIN0 */
#define CC2420_CSN_PORT(type) P##type##B
#define CC2420_CSN_PIN 0
/* - Output: VREG_EN to CC2420 - ATMEGA128 PORTA, PIN5 */
#define CC2420_VREG_PORT(type) P##type##A
#define CC2420_VREG_PIN 5
/* - Output: RESET_N to CC2420 - ATMEGA128 PORTA, PIN6 */
#define CC2420_RESET_PORT(type) P##type##A
#define CC2420_RESET_PIN 6
#define CC2420_IRQ_VECTOR INT6_vect
/* Pin status. */
#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
/* The CC2420 reset pin. */
#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(ORT) |= BV(CC2420_RESET_PIN))
#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(ORT) &= ~BV(CC2420_RESET_PIN))
/* CC2420 voltage regulator enable pin. */
#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(ORT) |= BV(CC2420_VREG_PIN))
#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(ORT) &= ~BV(CC2420_VREG_PIN))
/* CC2420 rising edge trigger for external interrupt 6 (FIFOP).
* Enable the external interrupt request for INT6.
* See Atmega128 datasheet about EICRB Register
*/
#define CC2420_FIFOP_INT_INIT() do {\
EICRB |= 0x30; \
CC2420_CLEAR_FIFOP_INT(); \
} while (0)
/* FIFOP on external interrupt 6. */
#define CC2420_ENABLE_FIFOP_INT() do { EIMSK |= 0x40; } while (0)
#define CC2420_DISABLE_FIFOP_INT() do { EIMSK &= ~0x40; } while (0)
#define CC2420_CLEAR_FIFOP_INT() do { EIFR = 0x40; } while (0)
/*
* Enables/disables CC2420 access to the SPI bus (not the bus).
* (Chip Select)
*/
#define CC2420_SPI_ENABLE() (PORTB &= ~BV(CSN)) /* ENABLE CSn (active low) */
#define CC2420_SPI_DISABLE() (PORTB |= BV(CSN)) /* DISABLE CSn (active low) */
#endif /* __PLATFORM_CONF_H__ */