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STM32F10x headers from FWLib

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This commit is contained in:
ksb 2009-07-12 16:41:53 +00:00
parent baa0dd90c9
commit 823bb613f3
6 changed files with 8320 additions and 1 deletions
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1
cpu/arm/stm32f103/Makefile.stm32f103
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@ -70,7 +70,6 @@ ARCH_FLAGS= -march=armv7-m -mthumb
CFLAGSNO = -I. -I$(CONTIKI)/core -I$(CONTIKI_CPU) -I$(CONTIKI_CPU)/loader \ CFLAGSNO = -I. -I$(CONTIKI)/core -I$(CONTIKI_CPU) -I$(CONTIKI_CPU)/loader \
-I$(CONTIKI_CPU)/dbg-io \ -I$(CONTIKI_CPU)/dbg-io \
-I$(CONTIKI_CPU)/FWLib/FWLib/library/inc/ \
-I$(CONTIKI)/platform/$(TARGET) \ -I$(CONTIKI)/platform/$(TARGET) \
${addprefix -I,$(APPDIRS)} \ ${addprefix -I,$(APPDIRS)} \
-DWITH_UIP -DWITH_ASCII -DMCK=$(MCK) \ -DWITH_UIP -DWITH_ASCII -DMCK=$(MCK) \

53
cpu/arm/stm32f103/cortexm3_macro.h Normal file
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@ -0,0 +1,53 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : cortexm3_macro.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : Header file for cortexm3_macro.s.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CORTEXM3_MACRO_H
#define __CORTEXM3_MACRO_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_type.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void __WFI(void);
void __WFE(void);
void __SEV(void);
void __ISB(void);
void __DSB(void);
void __DMB(void);
void __SVC(void);
u32 __MRS_CONTROL(void);
void __MSR_CONTROL(u32 Control);
u32 __MRS_PSP(void);
void __MSR_PSP(u32 TopOfProcessStack);
u32 __MRS_MSP(void);
void __MSR_MSP(u32 TopOfMainStack);
void __RESETPRIMASK(void);
void __SETPRIMASK(void);
u32 __READ_PRIMASK(void);
void __RESETFAULTMASK(void);
void __SETFAULTMASK(void);
u32 __READ_FAULTMASK(void);
void __BASEPRICONFIG(u32 NewPriority);
u32 __GetBASEPRI(void);
u16 __REV_HalfWord(u16 Data);
u32 __REV_Word(u32 Data);
#endif /* __CORTEXM3_MACRO_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

297
cpu/arm/stm32f103/stm32f10x_dma.h Normal file
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@ -0,0 +1,297 @@
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_dma.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DMA_H
#define __STM32F10x_DMA_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* DMA Init structure definition */
typedef struct
{
u32 DMA_PeripheralBaseAddr;
u32 DMA_MemoryBaseAddr;
u32 DMA_DIR;
u32 DMA_BufferSize;
u32 DMA_PeripheralInc;
u32 DMA_MemoryInc;
u32 DMA_PeripheralDataSize;
u32 DMA_MemoryDataSize;
u32 DMA_Mode;
u32 DMA_Priority;
u32 DMA_M2M;
}DMA_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
#define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \
((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \
((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE))
/* DMA data transfer direction -----------------------------------------------*/
#define DMA_DIR_PeripheralDST ((u32)0x00000010)
#define DMA_DIR_PeripheralSRC ((u32)0x00000000)
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
((DIR) == DMA_DIR_PeripheralSRC))
/* DMA peripheral incremented mode -------------------------------------------*/
#define DMA_PeripheralInc_Enable ((u32)0x00000040)
#define DMA_PeripheralInc_Disable ((u32)0x00000000)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
((STATE) == DMA_PeripheralInc_Disable))
/* DMA memory incremented mode -----------------------------------------------*/
#define DMA_MemoryInc_Enable ((u32)0x00000080)
#define DMA_MemoryInc_Disable ((u32)0x00000000)
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
((STATE) == DMA_MemoryInc_Disable))
/* DMA peripheral data size --------------------------------------------------*/
#define DMA_PeripheralDataSize_Byte ((u32)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100)
#define DMA_PeripheralDataSize_Word ((u32)0x00000200)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
((SIZE) == DMA_PeripheralDataSize_Word))
/* DMA memory data size ------------------------------------------------------*/
#define DMA_MemoryDataSize_Byte ((u32)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((u32)0x00000400)
#define DMA_MemoryDataSize_Word ((u32)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
((SIZE) == DMA_MemoryDataSize_Word))
/* DMA circular/normal mode --------------------------------------------------*/
#define DMA_Mode_Circular ((u32)0x00000020)
#define DMA_Mode_Normal ((u32)0x00000000)
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
/* DMA priority level --------------------------------------------------------*/
#define DMA_Priority_VeryHigh ((u32)0x00003000)
#define DMA_Priority_High ((u32)0x00002000)
#define DMA_Priority_Medium ((u32)0x00001000)
#define DMA_Priority_Low ((u32)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
/* DMA memory to memory ------------------------------------------------------*/
#define DMA_M2M_Enable ((u32)0x00004000)
#define DMA_M2M_Disable ((u32)0x00000000)
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
/* DMA interrupts definition -------------------------------------------------*/
#define DMA_IT_TC ((u32)0x00000002)
#define DMA_IT_HT ((u32)0x00000004)
#define DMA_IT_TE ((u32)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
/* For DMA1 */
#define DMA1_IT_GL1 ((u32)0x00000001)
#define DMA1_IT_TC1 ((u32)0x00000002)
#define DMA1_IT_HT1 ((u32)0x00000004)
#define DMA1_IT_TE1 ((u32)0x00000008)
#define DMA1_IT_GL2 ((u32)0x00000010)
#define DMA1_IT_TC2 ((u32)0x00000020)
#define DMA1_IT_HT2 ((u32)0x00000040)
#define DMA1_IT_TE2 ((u32)0x00000080)
#define DMA1_IT_GL3 ((u32)0x00000100)
#define DMA1_IT_TC3 ((u32)0x00000200)
#define DMA1_IT_HT3 ((u32)0x00000400)
#define DMA1_IT_TE3 ((u32)0x00000800)
#define DMA1_IT_GL4 ((u32)0x00001000)
#define DMA1_IT_TC4 ((u32)0x00002000)
#define DMA1_IT_HT4 ((u32)0x00004000)
#define DMA1_IT_TE4 ((u32)0x00008000)
#define DMA1_IT_GL5 ((u32)0x00010000)
#define DMA1_IT_TC5 ((u32)0x00020000)
#define DMA1_IT_HT5 ((u32)0x00040000)
#define DMA1_IT_TE5 ((u32)0x00080000)
#define DMA1_IT_GL6 ((u32)0x00100000)
#define DMA1_IT_TC6 ((u32)0x00200000)
#define DMA1_IT_HT6 ((u32)0x00400000)
#define DMA1_IT_TE6 ((u32)0x00800000)
#define DMA1_IT_GL7 ((u32)0x01000000)
#define DMA1_IT_TC7 ((u32)0x02000000)
#define DMA1_IT_HT7 ((u32)0x04000000)
#define DMA1_IT_TE7 ((u32)0x08000000)
/* For DMA2 */
#define DMA2_IT_GL1 ((u32)0x10000001)
#define DMA2_IT_TC1 ((u32)0x10000002)
#define DMA2_IT_HT1 ((u32)0x10000004)
#define DMA2_IT_TE1 ((u32)0x10000008)
#define DMA2_IT_GL2 ((u32)0x10000010)
#define DMA2_IT_TC2 ((u32)0x10000020)
#define DMA2_IT_HT2 ((u32)0x10000040)
#define DMA2_IT_TE2 ((u32)0x10000080)
#define DMA2_IT_GL3 ((u32)0x10000100)
#define DMA2_IT_TC3 ((u32)0x10000200)
#define DMA2_IT_HT3 ((u32)0x10000400)
#define DMA2_IT_TE3 ((u32)0x10000800)
#define DMA2_IT_GL4 ((u32)0x10001000)
#define DMA2_IT_TC4 ((u32)0x10002000)
#define DMA2_IT_HT4 ((u32)0x10004000)
#define DMA2_IT_TE4 ((u32)0x10008000)
#define DMA2_IT_GL5 ((u32)0x10010000)
#define DMA2_IT_TC5 ((u32)0x10020000)
#define DMA2_IT_HT5 ((u32)0x10040000)
#define DMA2_IT_TE5 ((u32)0x10080000)
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
/* DMA flags definition ------------------------------------------------------*/
/* For DMA1 */
#define DMA1_FLAG_GL1 ((u32)0x00000001)
#define DMA1_FLAG_TC1 ((u32)0x00000002)
#define DMA1_FLAG_HT1 ((u32)0x00000004)
#define DMA1_FLAG_TE1 ((u32)0x00000008)
#define DMA1_FLAG_GL2 ((u32)0x00000010)
#define DMA1_FLAG_TC2 ((u32)0x00000020)
#define DMA1_FLAG_HT2 ((u32)0x00000040)
#define DMA1_FLAG_TE2 ((u32)0x00000080)
#define DMA1_FLAG_GL3 ((u32)0x00000100)
#define DMA1_FLAG_TC3 ((u32)0x00000200)
#define DMA1_FLAG_HT3 ((u32)0x00000400)
#define DMA1_FLAG_TE3 ((u32)0x00000800)
#define DMA1_FLAG_GL4 ((u32)0x00001000)
#define DMA1_FLAG_TC4 ((u32)0x00002000)
#define DMA1_FLAG_HT4 ((u32)0x00004000)
#define DMA1_FLAG_TE4 ((u32)0x00008000)
#define DMA1_FLAG_GL5 ((u32)0x00010000)
#define DMA1_FLAG_TC5 ((u32)0x00020000)
#define DMA1_FLAG_HT5 ((u32)0x00040000)
#define DMA1_FLAG_TE5 ((u32)0x00080000)
#define DMA1_FLAG_GL6 ((u32)0x00100000)
#define DMA1_FLAG_TC6 ((u32)0x00200000)
#define DMA1_FLAG_HT6 ((u32)0x00400000)
#define DMA1_FLAG_TE6 ((u32)0x00800000)
#define DMA1_FLAG_GL7 ((u32)0x01000000)
#define DMA1_FLAG_TC7 ((u32)0x02000000)
#define DMA1_FLAG_HT7 ((u32)0x04000000)
#define DMA1_FLAG_TE7 ((u32)0x08000000)
/* For DMA2 */
#define DMA2_FLAG_GL1 ((u32)0x10000001)
#define DMA2_FLAG_TC1 ((u32)0x10000002)
#define DMA2_FLAG_HT1 ((u32)0x10000004)
#define DMA2_FLAG_TE1 ((u32)0x10000008)
#define DMA2_FLAG_GL2 ((u32)0x10000010)
#define DMA2_FLAG_TC2 ((u32)0x10000020)
#define DMA2_FLAG_HT2 ((u32)0x10000040)
#define DMA2_FLAG_TE2 ((u32)0x10000080)
#define DMA2_FLAG_GL3 ((u32)0x10000100)
#define DMA2_FLAG_TC3 ((u32)0x10000200)
#define DMA2_FLAG_HT3 ((u32)0x10000400)
#define DMA2_FLAG_TE3 ((u32)0x10000800)
#define DMA2_FLAG_GL4 ((u32)0x10001000)
#define DMA2_FLAG_TC4 ((u32)0x10002000)
#define DMA2_FLAG_HT4 ((u32)0x10004000)
#define DMA2_FLAG_TE4 ((u32)0x10008000)
#define DMA2_FLAG_GL5 ((u32)0x10010000)
#define DMA2_FLAG_TC5 ((u32)0x10020000)
#define DMA2_FLAG_HT5 ((u32)0x10040000)
#define DMA2_FLAG_TE5 ((u32)0x10080000)
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
/* DMA Buffer Size -----------------------------------------------------------*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState);
u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG);
void DMA_ClearFlag(u32 DMA_FLAG);
ITStatus DMA_GetITStatus(u32 DMA_IT);
void DMA_ClearITPendingBit(u32 DMA_IT);
#endif /*__STM32F10x_DMA_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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cpu/arm/stm32f103/stm32f10x_map.h Normal file
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cpu/arm/stm32f103/stm32f10x_nvic.h Normal file
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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_nvic.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the functions prototypes for the
* NVIC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_NVIC_H
#define __STM32F10x_NVIC_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
/* Exported types ------------------------------------------------------------*/
/* NVIC Init Structure definition */
typedef struct
{
u8 NVIC_IRQChannel;
u8 NVIC_IRQChannelPreemptionPriority;
u8 NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* IRQ Channels --------------------------------------------------------------*/
#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */
#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */
#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */
#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */
#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */
#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */
#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */
#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */
#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */
#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */
#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */
#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */
#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */
#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */
#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */
#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */
#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */
#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */
#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */
#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */
#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */
#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */
#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */
#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */
#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */
#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */
#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */
#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */
#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */
#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */
#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */
#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */
#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */
#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */
#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */
#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */
#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */
#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */
#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */
#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */
#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */
#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */
#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */
#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */
#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */
#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */
#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */
#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */
#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */
#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */
#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */
#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */
#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */
#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */
#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */
#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */
#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */
#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */
#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */
#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */
#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \
((CHANNEL) == PVD_IRQChannel) || \
((CHANNEL) == TAMPER_IRQChannel) || \
((CHANNEL) == RTC_IRQChannel) || \
((CHANNEL) == FLASH_IRQChannel) || \
((CHANNEL) == RCC_IRQChannel) || \
((CHANNEL) == EXTI0_IRQChannel) || \
((CHANNEL) == EXTI1_IRQChannel) || \
((CHANNEL) == EXTI2_IRQChannel) || \
((CHANNEL) == EXTI3_IRQChannel) || \
((CHANNEL) == EXTI4_IRQChannel) || \
((CHANNEL) == DMA1_Channel1_IRQChannel) || \
((CHANNEL) == DMA1_Channel2_IRQChannel) || \
((CHANNEL) == DMA1_Channel3_IRQChannel) || \
((CHANNEL) == DMA1_Channel4_IRQChannel) || \
((CHANNEL) == DMA1_Channel5_IRQChannel) || \
((CHANNEL) == DMA1_Channel6_IRQChannel) || \
((CHANNEL) == DMA1_Channel7_IRQChannel) || \
((CHANNEL) == ADC1_2_IRQChannel) || \
((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \
((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \
((CHANNEL) == CAN_RX1_IRQChannel) || \
((CHANNEL) == CAN_SCE_IRQChannel) || \
((CHANNEL) == EXTI9_5_IRQChannel) || \
((CHANNEL) == TIM1_BRK_IRQChannel) || \
((CHANNEL) == TIM1_UP_IRQChannel) || \
((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \
((CHANNEL) == TIM1_CC_IRQChannel) || \
((CHANNEL) == TIM2_IRQChannel) || \
((CHANNEL) == TIM3_IRQChannel) || \
((CHANNEL) == TIM4_IRQChannel) || \
((CHANNEL) == I2C1_EV_IRQChannel) || \
((CHANNEL) == I2C1_ER_IRQChannel) || \
((CHANNEL) == I2C2_EV_IRQChannel) || \
((CHANNEL) == I2C2_ER_IRQChannel) || \
((CHANNEL) == SPI1_IRQChannel) || \
((CHANNEL) == SPI2_IRQChannel) || \
((CHANNEL) == USART1_IRQChannel) || \
((CHANNEL) == USART2_IRQChannel) || \
((CHANNEL) == USART3_IRQChannel) || \
((CHANNEL) == EXTI15_10_IRQChannel) || \
((CHANNEL) == RTCAlarm_IRQChannel) || \
((CHANNEL) == USBWakeUp_IRQChannel) || \
((CHANNEL) == TIM8_BRK_IRQChannel) || \
((CHANNEL) == TIM8_UP_IRQChannel) || \
((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \
((CHANNEL) == TIM8_CC_IRQChannel) || \
((CHANNEL) == ADC3_IRQChannel) || \
((CHANNEL) == FSMC_IRQChannel) || \
((CHANNEL) == SDIO_IRQChannel) || \
((CHANNEL) == TIM5_IRQChannel) || \
((CHANNEL) == SPI3_IRQChannel) || \
((CHANNEL) == UART4_IRQChannel) || \
((CHANNEL) == UART5_IRQChannel) || \
((CHANNEL) == TIM6_IRQChannel) || \
((CHANNEL) == TIM7_IRQChannel) || \
((CHANNEL) == DMA2_Channel1_IRQChannel) || \
((CHANNEL) == DMA2_Channel2_IRQChannel) || \
((CHANNEL) == DMA2_Channel3_IRQChannel) || \
((CHANNEL) == DMA2_Channel4_5_IRQChannel))
/* System Handlers -----------------------------------------------------------*/
#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */
#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */
#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */
#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */
#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */
#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */
#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */
#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */
#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */
#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault))
#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_SVCall) || \
((HANDLER) == SystemHandler_DebugMonitor) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_SVCall))
#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_SVCall) || \
((HANDLER) == SystemHandler_DebugMonitor) || \
((HANDLER) == SystemHandler_PSV) || \
((HANDLER) == SystemHandler_SysTick))
#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \
((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault) || \
((HANDLER) == SystemHandler_UsageFault) || \
((HANDLER) == SystemHandler_DebugMonitor))
#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \
((HANDLER) == SystemHandler_BusFault))
/* Vector Table Base ---------------------------------------------------------*/
#define NVIC_VectTab_RAM ((u32)0x20000000)
#define NVIC_VectTab_FLASH ((u32)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/* System Low Power ----------------------------------------------------------*/
#define NVIC_LP_SEVONPEND ((u8)0x10)
#define NVIC_LP_SLEEPDEEP ((u8)0x04)
#define NVIC_LP_SLEEPONEXIT ((u8)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SETPRIMASK(void);
void NVIC_RESETPRIMASK(void);
void NVIC_SETFAULTMASK(void);
void NVIC_RESETFAULTMASK(void);
void NVIC_BASEPRICONFIG(u32 NewPriority);
u32 NVIC_GetBASEPRI(void);
u16 NVIC_GetCurrentPendingIRQChannel(void);
ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel);
void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel);
void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel);
u16 NVIC_GetCurrentActiveHandler(void);
ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel);
u32 NVIC_GetCPUID(void);
void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);
void NVIC_GenerateSystemReset(void);
void NVIC_GenerateCoreReset(void);
void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState);
void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState);
void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
u8 SystemHandlerSubPriority);
ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler);
void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler);
void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler);
ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler);
u32 NVIC_GetFaultHandlerSources(u32 SystemHandler);
u32 NVIC_GetFaultAddress(u32 SystemHandler);
#endif /* __STM32F10x_NVIC_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : stm32f10x_type.h
* Author : MCD Application Team
* Version : V2.0.3
* Date : 09/22/2008
* Description : This file contains all the common data types used for the
* STM32F10x firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_TYPE_H
#define __STM32F10x_TYPE_H
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
typedef signed long s32;
typedef signed short s16;
typedef signed char s8;
typedef signed long const sc32; /* Read Only */
typedef signed short const sc16; /* Read Only */
typedef signed char const sc8; /* Read Only */
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
typedef volatile signed long const vsc32; /* Read Only */
typedef volatile signed short const vsc16; /* Read Only */
typedef volatile signed char const vsc8; /* Read Only */
typedef unsigned long u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef unsigned long const uc32; /* Read Only */
typedef unsigned short const uc16; /* Read Only */
typedef unsigned char const uc8; /* Read Only */
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile unsigned long const vuc32; /* Read Only */
typedef volatile unsigned short const vuc16; /* Read Only */
typedef volatile unsigned char const vuc8; /* Read Only */
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define U8_MAX ((u8)255)
#define S8_MAX ((s8)127)
#define S8_MIN ((s8)-128)
#define U16_MAX ((u16)65535u)
#define S16_MAX ((s16)32767)
#define S16_MIN ((s16)-32768)
#define U32_MAX ((u32)4294967295uL)
#define S32_MAX ((s32)2147483647)
#define S32_MIN ((s32)-2147483648)
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
#endif /* __STM32F10x_TYPE_H */
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/