split hw config into platform-conf and adapted to new SPI and CC2420 naming
This commit is contained in:
joxe
parent
f7a82a9145
commit
80942abaf7
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@ -1,10 +1,10 @@
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/* -*- C -*- */
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/* @(#)$Id: contiki-conf.h,v 1.81 2010/06/21 19:57:18 joxe Exp $ */
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/* @(#)$Id: contiki-conf.h,v 1.82 2010/06/23 10:18:05 joxe Exp $ */
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#ifndef CONTIKI_CONF_H
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#define CONTIKI_CONF_H
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#include "platform-conf.h"
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#if WITH_UIP6
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@ -14,7 +14,6 @@
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/* #define NETSTACK_CONF_RDC sicslowmac_driver */
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#define NETSTACK_CONF_MAC csma_driver
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#define NETSTACK_CONF_RDC contikimac_driver
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#define NETSTACK_CONF_RADIO cc2420_driver
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#define NETSTACK_CONF_FRAMER framer_802154
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#define CC2420_CONF_AUTOACK 1
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@ -32,7 +31,6 @@
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#define NETSTACK_CONF_NETWORK rime_driver
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#define NETSTACK_CONF_MAC csma_driver
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#define NETSTACK_CONF_RDC contikimac_driver
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#define NETSTACK_CONF_RADIO cc2420_driver
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#define NETSTACK_CONF_FRAMER framer_802154
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#define CC2420_CONF_AUTOACK 1
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@ -56,7 +54,6 @@
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#define PACKETBUF_CONF_ATTRS_INLINE 1
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#define CC2420_CONF_SYMBOL_LOOP_COUNT 800
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#ifndef RF_CHANNEL
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#define RF_CHANNEL 26
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#endif /* RF_CHANNEL */
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@ -68,52 +65,22 @@
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#define SHELL_VARS_CONF_RAM_BEGIN 0x1100
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#define SHELL_VARS_CONF_RAM_END 0x2000
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/* DCO speed resynchronization for more robust UART, etc. */
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#define DCOSYNCH_CONF_ENABLED 1
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#define DCOSYNCH_CONF_PERIOD 30
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#define CFS_CONF_OFFSET_TYPE long
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#define PROFILE_CONF_ON 0
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#define ENERGEST_CONF_ON 1
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#define HAVE_STDINT_H
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#define MSP430_MEMCPY_WORKAROUND 1
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#include "msp430def.h"
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#define ELFLOADER_CONF_TEXT_IN_ROM 0
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#define ELFLOADER_CONF_DATAMEMORY_SIZE 0x400
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#define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x800
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#define IRQ_PORT1 0x01
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#define IRQ_PORT2 0x02
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#define IRQ_ADC 0x03
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#define CCIF
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#define CLIF
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#define CC_CONF_INLINE inline
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#define AODV_COMPLIANCE
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#define AODV_NUM_RT_ENTRIES 32
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#define TMOTE_SKY 1
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#define WITH_ASCII 1
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#define PROCESS_CONF_NUMEVENTS 8
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#define PROCESS_CONF_STATS 1
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/*#define PROCESS_CONF_FASTPOLL 4*/
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/* CPU target speed in Hz */
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#define F_CPU 3900000uL /*2457600uL*/
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/* Our clock resolution, this is the same as Unix HZ. */
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#define CLOCK_CONF_SECOND 128UL
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#define BAUD2UBR(baud) ((F_CPU/baud))
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#ifdef WITH_UIP6
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#define RIMEADDR_CONF_SIZE 8
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@ -177,127 +144,6 @@
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#define UIP_CONF_TCP_SPLIT 0
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/*
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* Definitions below are dictated by the hardware and not really
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* changeable!
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*/
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/* LED ports */
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#define LEDS_PxDIR P5DIR
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#define LEDS_PxOUT P5OUT
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#define LEDS_CONF_RED 0x10
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#define LEDS_CONF_GREEN 0x20
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#define LEDS_CONF_YELLOW 0x40
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/* Button sensors. */
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#define IRQ_PORT2 0x02
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typedef unsigned short uip_stats_t;
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typedef unsigned long clock_time_t;
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typedef unsigned long off_t;
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#define ROM_ERASE_UNIT_SIZE 512
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#define XMEM_ERASE_UNIT_SIZE (64*1024L)
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/* Use the first 64k of external flash for node configuration */
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#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
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/* Use the second 64k of external flash for codeprop. */
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#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_RAM_CONF_SIZE 4096
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/*
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* SPI bus configuration for the TMote Sky.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF U0TXBUF
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#define SPI_RXBUF U0RXBUF
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/* USART0 Tx ready? */
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#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
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/* USART0 Rx ready? */
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#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
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/* USART0 Tx buffer ready? */
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#define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
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#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
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#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
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#define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
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/*
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* SPI bus - M25P80 external flash configuration.
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*/
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#define FLASH_PWR 3 /* P4.3 Output */
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#define FLASH_CS 4 /* P4.4 Output */
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#define FLASH_HOLD 7 /* P4.7 Output */
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/* Enable/disable flash access to the SPI bus (active low). */
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#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
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#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
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#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
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#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
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/*
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* SPI bus - CC2420 pin configuration.
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*/
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#define FIFO_P 0 /* P1.0 - Input: FIFOP from CC2420 */
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#define FIFO 3 /* P1.3 - Input: FIFO from CC2420 */
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#define CCA 4 /* P1.4 - Input: CCA from CC2420 */
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#define SFD 1 /* P4.1 - Input: SFD from CC2420 */
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#define CSN 2 /* P4.2 - Output: SPI Chip Select (CS_N) */
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#define VREG_EN 5 /* P4.5 - Output: VREG_EN to CC2420 */
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#define RESET_N 6 /* P4.6 - Output: RESET_N to CC2420 */
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/* Pin status. */
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#define FIFO_IS_1 (!!(P1IN & BV(FIFO)))
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#define CCA_IS_1 (!!(P1IN & BV(CCA) ))
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#define RESET_IS_1 (!!(P4IN & BV(RESET_N)))
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#define VREG_IS_1 (!!(P4IN & BV(VREG_EN)))
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#define FIFOP_IS_1 (!!(P1IN & BV(FIFO_P)))
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#define SFD_IS_1 (!!(P4IN & BV(SFD)))
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/* The CC2420 reset pin. */
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#define SET_RESET_INACTIVE() ( P4OUT |= BV(RESET_N) )
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#define SET_RESET_ACTIVE() ( P4OUT &= ~BV(RESET_N) )
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/* CC2420 voltage regulator enable pin. */
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#define SET_VREG_ACTIVE() ( P4OUT |= BV(VREG_EN) )
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#define SET_VREG_INACTIVE() ( P4OUT &= ~BV(VREG_EN) )
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/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
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#define FIFOP_INT_INIT() do {\
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P1IES &= ~BV(FIFO_P);\
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CLEAR_FIFOP_INT();\
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} while (0)
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/* FIFOP on external interrupt 0. */
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#define ENABLE_FIFOP_INT() do { P1IE |= BV(FIFO_P); } while (0)
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#define DISABLE_FIFOP_INT() do { P1IE &= ~BV(FIFO_P); } while (0)
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#define CLEAR_FIFOP_INT() do { P1IFG &= ~BV(FIFO_P); } while (0)
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/* Enables/disables CC2420 access to the SPI bus (not the bus).
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*
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* These guys should really be renamed but are compatible with the
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* original Chipcon naming.
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*
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* SPI_CC2420_ENABLE/SPI_CC2420_DISABLE???
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* CC2420_ENABLE_SPI/CC2420_DISABLE_SPI???
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*/
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#define SPI_ENABLE() ( P4OUT &= ~BV(CSN) ) /* ENABLE CSn (active low) */
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#define SPI_DISABLE() ( P4OUT |= BV(CSN) ) /* DISABLE CSn (active low) */
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#define SPI_IS_ENABLED() ( (P4OUT & BV(CSN)) != BV(CSN) )
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#ifdef PROJECT_CONF_H
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#include PROJECT_CONF_H
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@ -26,7 +26,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)$Id: xmem.c,v 1.10 2009/09/07 11:31:26 nifi Exp $
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* @(#)$Id: xmem.c,v 1.11 2010/06/23 10:18:05 joxe Exp $
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*/
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/**
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@ -77,8 +77,7 @@ write_enable(void)
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s = splhigh();
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SPI_FLASH_ENABLE();
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FASTSPI_TX(SPI_FLASH_INS_WREN);
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SPI_WAITFORTx_ENDED();
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SPI_WRITE(SPI_FLASH_INS_WREN);
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SPI_FLASH_DISABLE();
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splx(s);
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s = splhigh();
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SPI_FLASH_ENABLE();
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FASTSPI_TX(SPI_FLASH_INS_RDSR);
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SPI_WAITFORTx_ENDED();
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SPI_WRITE(SPI_FLASH_INS_RDSR);
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FASTSPI_CLEAR_RX();
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FASTSPI_RX(u);
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SPI_FLUSH();
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SPI_READ(u);
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SPI_FLASH_DISABLE();
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splx(s);
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s = splhigh();
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SPI_FLASH_ENABLE();
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FASTSPI_TX(SPI_FLASH_INS_SE);
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FASTSPI_TX(offset >> 16); /* MSB */
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FASTSPI_TX(offset >> 8);
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FASTSPI_TX(offset >> 0); /* LSB */
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SPI_WRITE_FAST(SPI_FLASH_INS_SE);
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SPI_WRITE_FAST(offset >> 16); /* MSB */
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SPI_WRITE_FAST(offset >> 8);
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SPI_WRITE_FAST(offset >> 0); /* LSB */
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SPI_WAITFORTx_ENDED();
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SPI_FLASH_DISABLE();
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@ -171,16 +169,16 @@ xmem_pread(void *_p, int size, unsigned long offset)
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s = splhigh();
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SPI_FLASH_ENABLE();
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FASTSPI_TX(SPI_FLASH_INS_READ);
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FASTSPI_TX(offset >> 16); /* MSB */
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FASTSPI_TX(offset >> 8);
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FASTSPI_TX(offset >> 0); /* LSB */
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SPI_WRITE_FAST(SPI_FLASH_INS_READ);
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SPI_WRITE_FAST(offset >> 16); /* MSB */
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SPI_WRITE_FAST(offset >> 8);
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SPI_WRITE_FAST(offset >> 0); /* LSB */
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SPI_WAITFORTx_ENDED();
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FASTSPI_CLEAR_RX();
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SPI_FLUSH();
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for(; p < end; p++) {
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unsigned char u;
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FASTSPI_RX(u);
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SPI_READ(u);
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*p = ~u;
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}
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@ -205,13 +203,13 @@ program_page(unsigned long offset, const unsigned char *p, int nbytes)
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s = splhigh();
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SPI_FLASH_ENABLE();
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FASTSPI_TX(SPI_FLASH_INS_PP);
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FASTSPI_TX(offset >> 16); /* MSB */
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FASTSPI_TX(offset >> 8);
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FASTSPI_TX(offset >> 0); /* LSB */
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SPI_WRITE_FAST(SPI_FLASH_INS_PP);
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SPI_WRITE_FAST(offset >> 16); /* MSB */
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SPI_WRITE_FAST(offset >> 8);
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SPI_WRITE_FAST(offset >> 0); /* LSB */
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for(; p < end; p++) {
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FASTSPI_TX(~*p);
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SPI_WRITE_FAST(~*p);
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}
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SPI_WAITFORTx_ENDED();
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206
platform/sky/platform-conf.h
Normal file
206
platform/sky/platform-conf.h
Normal file
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@ -0,0 +1,206 @@
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/*
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* Copyright (c) 2010, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: platform-conf.h,v 1.1 2010/06/23 10:18:05 joxe Exp $
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*/
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/**
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* \file
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* A brief description of what this file is
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* \author
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* Niclas Finne <nfi@sics.se>
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* Joakim Eriksson <joakime@sics.se>
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*/
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#ifndef __PLATFORM_CONF_H__
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#define __PLATFORM_CONF_H__
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/*
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* Definitions below are dictated by the hardware and not really
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* changeable!
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*/
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/* Platform TMOTE_SKY */
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#define TMOTE_SKY 1
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/* CPU target speed in Hz */
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#define F_CPU 3900000uL /*2457600uL*/
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/* Our clock resolution, this is the same as Unix HZ. */
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#define CLOCK_CONF_SECOND 128UL
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#define BAUD2UBR(baud) ((F_CPU/baud))
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#define CCIF
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#define CLIF
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#define CC_CONF_INLINE inline
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#define HAVE_STDINT_H
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#define MSP430_MEMCPY_WORKAROUND 1
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#include "msp430def.h"
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/* Types for clocks and uip_stats */
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typedef unsigned short uip_stats_t;
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typedef unsigned long clock_time_t;
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typedef unsigned long off_t;
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/* the low-level radio driver */
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#define NETSTACK_CONF_RADIO cc2420_driver
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/* LED ports */
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#define LEDS_PxDIR P5DIR
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#define LEDS_PxOUT P5OUT
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#define LEDS_CONF_RED 0x10
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#define LEDS_CONF_GREEN 0x20
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#define LEDS_CONF_YELLOW 0x40
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/* DCO speed resynchronization for more robust UART, etc. */
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#define DCOSYNCH_CONF_ENABLED 1
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#define DCOSYNCH_CONF_PERIOD 30
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#define ROM_ERASE_UNIT_SIZE 512
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#define XMEM_ERASE_UNIT_SIZE (64*1024L)
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#define CFS_CONF_OFFSET_TYPE long
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/* Use the first 64k of external flash for node configuration */
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#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
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/* Use the second 64k of external flash for codeprop. */
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#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_RAM_CONF_SIZE 4096
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/*
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* SPI bus configuration for the TMote Sky.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF U0TXBUF
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#define SPI_RXBUF U0RXBUF
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/* USART0 Tx ready? */
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#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
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/* USART0 Rx ready? */
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#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
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/* USART0 Tx buffer ready? */
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#define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
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#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
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#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
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#define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
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/*
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* SPI bus - M25P80 external flash configuration.
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*/
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#define FLASH_PWR 3 /* P4.3 Output */
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#define FLASH_CS 4 /* P4.4 Output */
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#define FLASH_HOLD 7 /* P4.7 Output */
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/* Enable/disable flash access to the SPI bus (active low). */
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#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
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#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
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#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
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#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
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/*
|
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* SPI bus - CC2420 pin configuration.
|
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*/
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#define CC2420_CONF_SYMBOL_LOOP_COUNT 800
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/* P1.0 - Input: FIFOP from CC2420 */
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#define CC2420_FIFOP_PORT(type) P1##type
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#define CC2420_FIFOP_PIN 0
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/* P1.3 - Input: FIFO from CC2420 */
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#define CC2420_FIFO_PORT(type) P1##type
|
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#define CC2420_FIFO_PIN 3
|
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/* P1.4 - Input: CCA from CC2420 */
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#define CC2420_CCA_PORT(type) P1##type
|
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#define CC2420_CCA_PIN 4
|
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/* P4.1 - Input: SFD from CC2420 */
|
||||
#define CC2420_SFD_PORT(type) P4##type
|
||||
#define CC2420_SFD_PIN 1
|
||||
/* P4.2 - Output: SPI Chip Select (CS_N) */
|
||||
#define CC2420_CSN_PORT(type) P4##type
|
||||
#define CC2420_CSN_PIN 2
|
||||
/* P4.5 - Output: VREG_EN to CC2420 */
|
||||
#define CC2420_VREG_PORT(type) P4##type
|
||||
#define CC2420_VREG_PIN 5
|
||||
/* P4.6 - Output: RESET_N to CC2420 */
|
||||
#define CC2420_RESET_PORT(type) P4##type
|
||||
#define CC2420_RESET_PIN 6
|
||||
|
||||
#define CC2420_IRQ_VECTOR PORT1_VECTOR
|
||||
|
||||
/* Pin status. */
|
||||
#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
|
||||
#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
|
||||
#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
|
||||
#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
|
||||
|
||||
/* The CC2420 reset pin. */
|
||||
#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
|
||||
#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
|
||||
|
||||
/* CC2420 voltage regulator enable pin. */
|
||||
#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
|
||||
#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
|
||||
|
||||
/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
|
||||
#define CC2420_FIFOP_INT_INIT() do { \
|
||||
CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
|
||||
CC2420_CLEAR_FIFOP_INT(); \
|
||||
} while(0)
|
||||
|
||||
/* FIFOP on external interrupt 0. */
|
||||
#define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
|
||||
#define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
|
||||
#define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
|
||||
|
||||
/*
|
||||
* Enables/disables CC2420 access to the SPI bus (not the bus).
|
||||
* (Chip Select)
|
||||
*/
|
||||
|
||||
/* ENABLE CSn (active low) */
|
||||
#define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
|
||||
/* DISABLE CSn (active low) */
|
||||
#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
|
||||
#define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
|
||||
|
||||
#endif /* __PLATFORM_CONF_H__ */
|
||||
Loading…
Reference in a new issue