Merge pull request #328 from g-oikonomou/cc2538-uart-config
Make the CC2538 UART driver more configurable
This commit is contained in:
Nicolas Tsiftes
commit
7987a6dac7
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@ -48,49 +48,82 @@
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static int (* input_handler)(unsigned char c);
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/*---------------------------------------------------------------------------*/
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/*
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* Once we know what UART we're on, configure correct values to be written to
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* the correct registers
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*/
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#if UART_BASE==UART_1_BASE
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/* Running, in sleep, in deep sleep, enable the clock for the correct UART */
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#define SYS_CTRL_RCGCUART_UART SYS_CTRL_RCGCUART_UART1
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#define SYS_CTRL_SCGCUART_UART SYS_CTRL_SCGCUART_UART1
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#define SYS_CTRL_DCGCUART_UART SYS_CTRL_DCGCUART_UART1
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#define NVIC_INT_UART NVIC_INT_UART1
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#define IOC_PXX_SEL_UART_TXD IOC_PXX_SEL_UART1_TXD
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#define IOC_UARTRXD_UART IOC_UARTRXD_UART1
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#else /* Defaults for UART0 */
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#define SYS_CTRL_RCGCUART_UART SYS_CTRL_RCGCUART_UART0
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#define SYS_CTRL_SCGCUART_UART SYS_CTRL_SCGCUART_UART0
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#define SYS_CTRL_DCGCUART_UART SYS_CTRL_DCGCUART_UART0
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#define NVIC_INT_UART NVIC_INT_UART0
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#define IOC_PXX_SEL_UART_TXD IOC_PXX_SEL_UART0_TXD
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#define IOC_UARTRXD_UART IOC_UARTRXD_UART0
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#endif
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/*---------------------------------------------------------------------------*/
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static void
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reset(void)
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{
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uint32_t lchr;
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/* Make sure the UART is disabled before trying to configure it */
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REG(UART_0_BASE | UART_CTL) = UART_CTL_TXE | UART_CTL_RXE;
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REG(UART_BASE | UART_CTL) = UART_CTL_TXE | UART_CTL_RXE;
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/* Clear error status */
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REG(UART_0_BASE | UART_ECR) = 0xFF;
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REG(UART_BASE | UART_ECR) = 0xFF;
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/* Store LCHR configuration */
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lchr = REG(UART_0_BASE | UART_LCRH);
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lchr = REG(UART_BASE | UART_LCRH);
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/* Flush FIFOs by clearing LCHR.FEN */
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REG(UART_0_BASE | UART_LCRH) = 0;
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REG(UART_BASE | UART_LCRH) = 0;
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/* Restore LCHR configuration */
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REG(UART_0_BASE | UART_LCRH) = lchr;
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REG(UART_BASE | UART_LCRH) = lchr;
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/* UART Enable */
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REG(UART_0_BASE | UART_CTL) |= UART_CTL_UARTEN;
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REG(UART_BASE | UART_CTL) |= UART_CTL_UARTEN;
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}
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/*---------------------------------------------------------------------------*/
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void
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uart_init(void)
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{
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/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
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REG(SYS_CTRL_RCGCUART) |= SYS_CTRL_RCGCUART_UART0;
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REG(SYS_CTRL_SCGCUART) |= SYS_CTRL_DCGCUART_UART0;
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REG(SYS_CTRL_DCGCUART) |= SYS_CTRL_DCGCUART_UART0;
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REG(SYS_CTRL_RCGCUART) |= SYS_CTRL_RCGCUART_UART;
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REG(SYS_CTRL_SCGCUART) |= SYS_CTRL_SCGCUART_UART;
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REG(SYS_CTRL_DCGCUART) |= SYS_CTRL_DCGCUART_UART;
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/* Run on SYS_DIV */
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REG(UART_0_BASE | UART_CC) = 0;
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REG(UART_BASE | UART_CC) = 0;
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/* PA1: UART TX */
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REG(IOC_PA1_SEL) = IOC_PXX_SEL_UART0_TXD;
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/*
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* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
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*
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* The value to be written will be on of the IOC_INPUT_SEL_Pxn defines from
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* ioc.h. The value can also be calculated as:
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*
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* (port << 3) + pin
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*/
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REG(IOC_UARTRXD_UART) = (UART_RX_PORT << 3) + UART_RX_PIN;
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/* PA0: UART RX */
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REG(IOC_UARTRXD_UART0) = IOC_INPUT_SEL_PA0;
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/* Pad Control: PA1 Output Enable */
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REG(IOC_PA1_OVER) = IOC_OVERRIDE_OE;
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/*
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* Pad Control for the TX pin:
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* - Set function to UART0 TX
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* - Output Enable
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*/
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ioc_set_sel(UART_TX_PORT, UART_TX_PIN, IOC_PXX_SEL_UART_TXD);
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ioc_set_over(UART_TX_PORT, UART_TX_PIN, IOC_OVERRIDE_OE);
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/* Set PA[1:0] to peripheral mode */
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REG(GPIO_A_BASE | GPIO_AFSEL) |= (0x00000002 | 0x00000001);
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@ -100,27 +133,27 @@ uart_init(void)
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* Acknowledge RX and RX Timeout
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* Acknowledge Framing, Overrun and Break Errors
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*/
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REG(UART_0_BASE | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
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REG(UART_0_BASE | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
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REG(UART_BASE | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
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REG(UART_BASE | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
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REG(UART_0_BASE | UART_IFLS) =
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REG(UART_BASE | UART_IFLS) =
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UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
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/* Make sure the UART is disabled before trying to configure it */
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REG(UART_0_BASE | UART_CTL) = UART_CTL_TXE | UART_CTL_RXE;
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REG(UART_BASE | UART_CTL) = UART_CTL_TXE | UART_CTL_RXE;
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/* Baud Rate Generation */
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REG(UART_0_BASE | UART_IBRD) = UART_CONF_IBRD;
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REG(UART_0_BASE | UART_FBRD) = UART_CONF_FBRD;
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REG(UART_BASE | UART_IBRD) = UART_CONF_IBRD;
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REG(UART_BASE | UART_FBRD) = UART_CONF_FBRD;
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/* UART Control: 8N1 with FIFOs */
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REG(UART_0_BASE | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
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REG(UART_BASE | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
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/* UART Enable */
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REG(UART_0_BASE | UART_CTL) |= UART_CTL_UARTEN;
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REG(UART_BASE | UART_CTL) |= UART_CTL_UARTEN;
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/* Enable UART0 Interrupts */
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nvic_interrupt_enable(NVIC_INT_UART0);
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nvic_interrupt_enable(NVIC_INT_UART);
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}
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/*---------------------------------------------------------------------------*/
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void
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@ -133,9 +166,9 @@ void
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uart_write_byte(uint8_t b)
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{
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/* Block if the TX FIFO is full */
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while(REG(UART_0_BASE | UART_FR) & UART_FR_TXFF);
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while(REG(UART_BASE | UART_FR) & UART_FR_TXFF);
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REG(UART_0_BASE | UART_DR) = b;
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REG(UART_BASE | UART_DR) = b;
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}
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/*---------------------------------------------------------------------------*/
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void
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@ -147,18 +180,18 @@ uart_isr(void)
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/* Store the current MIS and clear all flags early, except the RTM flag.
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* This will clear itself when we read out the entire FIFO contents */
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mis = REG(UART_0_BASE | UART_MIS) & 0x0000FFFF;
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mis = REG(UART_BASE | UART_MIS) & 0x0000FFFF;
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REG(UART_0_BASE | UART_ICR) = 0x0000FFBF;
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REG(UART_BASE | UART_ICR) = 0x0000FFBF;
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if(mis & (UART_MIS_RXMIS | UART_MIS_RTMIS)) {
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while(!(REG(UART_0_BASE | UART_FR) & UART_FR_RXFE)) {
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while(!(REG(UART_BASE | UART_FR) & UART_FR_RXFE)) {
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if(input_handler != NULL) {
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input_handler((unsigned char)(REG(UART_0_BASE | UART_DR) & 0xFF));
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input_handler((unsigned char)(REG(UART_BASE | UART_DR) & 0xFF));
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} else {
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/* To prevent an Overrun Error, we need to flush the FIFO even if we
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* don't have an input_handler. Use mis as a data trash can */
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mis = REG(UART_0_BASE | UART_DR);
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mis = REG(UART_BASE | UART_DR);
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}
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}
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} else if(mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_FEMIS)) {
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@ -52,6 +52,13 @@
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*/
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#define UART_0_BASE 0x4000C000
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#define UART_1_BASE 0x4000D000
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/* Default to UART 0 unless the configuration tells us otherwise */
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#ifdef UART_CONF_BASE
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#define UART_BASE UART_CONF_BASE
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#else
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#define UART_BASE UART_0_BASE
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#endif
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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@ -111,8 +111,11 @@
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* - CTS: PB0 (Can only be used with UART1)
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* - RTS: PD3 (Can only be used with UART1)
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*
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* We configure the port to use UART0. To use UART1, change UART_CONF_BASE
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* @{
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*/
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#define UART_CONF_BASE UART_0_BASE
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#define UART_RX_PORT GPIO_A_NUM
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#define UART_RX_PIN 0
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@ -38,6 +38,7 @@
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*/
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#include "contiki.h"
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#include "reg.h"
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#include "uart.h"
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#include <stdint.h>
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@ -71,12 +72,22 @@ void usb_isr(void);
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#define usb_isr default_handler
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#endif
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/* Likewise for the UART ISR */
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/* Likewise for the UART[01] ISRs */
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#if UART_CONF_ENABLE
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void uart_isr(void);
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#if UART_BASE==UART_1_BASE
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#define uart0_isr default_handler
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#define uart1_isr uart_isr
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#else
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#define uart_isr default_handler
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#define uart0_isr uart_isr
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#define uart1_isr default_handler
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#endif
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#else /* UART_CONF_ENABLE */
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#define uart0_isr default_handler
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#define uart1_isr default_handler
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#endif /* UART_CONF_ENABLE */
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/*---------------------------------------------------------------------------*/
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/* Allocate stack space */
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static unsigned long stack[512];
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@ -123,8 +134,8 @@ void(*const vectors[])(void) =
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gpio_port_c_isr, /* 18 GPIO Port C */
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gpio_port_d_isr, /* 19 GPIO Port D */
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0, /* 20 none */
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uart_isr, /* 21 UART0 Rx and Tx */
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default_handler, /* 22 UART1 Rx and Tx */
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uart0_isr, /* 21 UART0 Rx and Tx */
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uart1_isr, /* 22 UART1 Rx and Tx */
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default_handler, /* 23 SSI0 Rx and Tx */
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default_handler, /* 24 I2C Master and Slave */
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0, /* 25 Reserved */
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