mc1322x: flush the rx fifos when full

This commit is contained in:
Mariano Alvira 2011-07-12 07:05:04 -04:00
parent 6355545ded
commit 758fc37307
2 changed files with 28 additions and 24 deletions

View file

@ -47,19 +47,21 @@ volatile uint32_t u1_rx_head, u1_rx_tail;
void uart1_isr(void) {
#if UART1_RX_BUFFERSIZE > 32
if (*UART1_USTAT & ( 1 << 6)) { //receive interrupt
while( *UART1_URXCON != 0 ) { //flush the hardware fifo into the software buffer
uint32_t u1_rx_tail_next;
u1_rx_tail_next = u1_rx_tail+1;
if (u1_rx_tail_next >= sizeof(u1_rx_buf))
u1_rx_tail_next = 0;
if (u1_rx_head != u1_rx_tail_next) {
u1_rx_buf[u1_rx_tail]= *UART1_UDATA;
u1_rx_tail = u1_rx_tail_next;
}
if (*UART1_USTAT & ( 1 << 6)) { //receive interrupt
while( *UART1_URXCON != 0 ) { //flush the hardware fifo into the software buffer
uint32_t u1_rx_tail_next;
u1_rx_tail_next = u1_rx_tail+1;
if (u1_rx_tail_next >= sizeof(u1_rx_buf))
u1_rx_tail_next = 0;
if (u1_rx_head != u1_rx_tail_next) {
u1_rx_buf[u1_rx_tail]= *UART1_UDATA;
u1_rx_tail = u1_rx_tail_next;
} else { //buffer is full, flush the fifo
while (*UART1_URXCON !=0) if (*UART1_UDATA);
}
}
return;
}
return;
}
#endif
while( *UART1_UTXCON != 0 ) {

View file

@ -47,19 +47,21 @@ volatile uint32_t u2_rx_head, u2_rx_tail;
void uart2_isr(void) {
#if UART2_RX_BUFFERSIZE > 32
if (*UART2_USTAT & ( 1 << 6)) { //receive interrupt
while( *UART2_URXCON != 0 ) { //flush the hardware fifo into the software buffer
uint32_t u2_rx_tail_next;
u2_rx_tail_next = u2_rx_tail+1;
if (u2_rx_tail_next >= sizeof(u2_rx_buf))
u2_rx_tail_next = 0;
if (u2_rx_head != u2_rx_tail_next) {
u2_rx_buf[u2_rx_tail]= *UART2_UDATA;
u2_rx_tail = u2_rx_tail_next;
}
if (*UART2_USTAT & ( 1 << 6)) { //receive interrupt
while( *UART2_URXCON != 0 ) { //flush the hardware fifo into the software buffer
uint32_t u2_rx_tail_next;
u2_rx_tail_next = u2_rx_tail+1;
if (u2_rx_tail_next >= sizeof(u2_rx_buf))
u2_rx_tail_next = 0;
if (u2_rx_head != u2_rx_tail_next) {
u2_rx_buf[u2_rx_tail]= *UART2_UDATA;
u2_rx_tail = u2_rx_tail_next;
} else { //buffer is full, flush the fifo
while (*UART2_URXCON !=0) if (*UART2_UDATA);
}
}
return;
}
return;
}
#endif
while( *UART2_UTXCON != 0 ) {