Merge pull request #1376 from sumanpanchal/wismote-uart1-dma
Wismote : Direct memory access using UART.
This commit is contained in:
commit
6def22b3c5
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@ -44,6 +44,36 @@ static int (*uart1_input_handler)(unsigned char c);
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static volatile uint8_t transmitting;
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static volatile uint8_t transmitting;
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#ifdef UART1_CONF_RX_WITH_DMA
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#define RX_WITH_DMA UART1_CONF_RX_WITH_DMA
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#else /* UART1_CONF_RX_WITH_DMA */
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#define RX_WITH_DMA 1
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#endif /* UART1_CONF_RX_WITH_DMA */
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#if RX_WITH_DMA
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#define RXBUFSIZE 128
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static uint8_t rxbuf[RXBUFSIZE];
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static uint16_t last_size;
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static struct ctimer rxdma_timer;
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static void
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handle_rxdma_timer(void *ptr)
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{
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uint16_t size;
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size = DMA0SZ; /* Note: loop requires that size is less or eq to RXBUFSIZE */
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while(last_size != size) {
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uart1_input_handler((unsigned char)rxbuf[RXBUFSIZE - last_size]);
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last_size--;
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if(last_size == 0) {
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last_size = RXBUFSIZE;
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}
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}
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ctimer_reset(&rxdma_timer);
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}
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#endif /* RX_WITH_DMA */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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uint8_t
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uint8_t
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uart1_active(void)
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uart1_active(void)
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@ -54,6 +84,9 @@ uart1_active(void)
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void
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void
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uart1_set_input(int (*input)(unsigned char c))
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uart1_set_input(int (*input)(unsigned char c))
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{
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{
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#if RX_WITH_DMA /* This needs to be called after ctimer process is started */
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ctimer_set(&rxdma_timer, CLOCK_SECOND / 64, handle_rxdma_timer, NULL);
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#endif
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uart1_input_handler = input;
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uart1_input_handler = input;
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@ -86,8 +119,8 @@ uart1_init(unsigned long ubr)
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UCA1MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
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UCA1MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
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P4DIR |= BIT5;
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P4DIR |= BIT5;
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P4OUT |= BIT5 ;
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P4OUT |= BIT5;
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P5SEL |= BIT6|BIT7; // P5.6,7 = USCI_A1 TXD/RXD
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P5SEL |= BIT6 | BIT7; /* P5.6,7 = USCI_A1 TXD/RXD */
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P4SEL |= BIT7;
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P4SEL |= BIT7;
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P4DIR |= BIT7;
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P4DIR |= BIT7;
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@ -102,14 +135,30 @@ uart1_init(unsigned long ubr)
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UCA1CTL1 &= ~UCSWRST; /* Initialize USCI state machine **before** enabling interrupts */
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UCA1CTL1 &= ~UCSWRST; /* Initialize USCI state machine **before** enabling interrupts */
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UCA1IE |= UCRXIE; /* Enable UCA1 RX interrupt */
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UCA1IE |= UCRXIE; /* Enable UCA1 RX interrupt */
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#if RX_WITH_DMA
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UCA1IE &= ~UCRXIE; /* disable USART1 RX interrupt */
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/* UART1_RX trigger */
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DMACTL0 = DMA0TSEL_20;
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/* source address = RXBUF1 */
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DMA0SA = (unsigned int)&UCA1RXBUF;
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DMA0DA = (unsigned int)&rxbuf;
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DMA0SZ = RXBUFSIZE;
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last_size = RXBUFSIZE;
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DMA0CTL = DMADT_4 + DMASBDB + DMADSTINCR_3 + DMAEN + DMAREQ;
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msp430_add_lpm_req(MSP430_REQUIRE_LPM1);
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#endif /* RX_WITH_DMA */
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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#if !RX_WITH_DMA
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ISR(USCI_A1, uart1_rx_interrupt)
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ISR(USCI_A1, uart1_rx_interrupt)
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{
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{
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uint8_t c;
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uint8_t c;
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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if (UCA1IV == 2) {
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if(UCA1IV == 2) {
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if(UCA1STAT & UCRXERR) {
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if(UCA1STAT & UCRXERR) {
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c = UCA1RXBUF; /* Clear error flags by forcing a dummy read. */
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c = UCA1RXBUF; /* Clear error flags by forcing a dummy read. */
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} else {
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} else {
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@ -123,4 +172,5 @@ ISR(USCI_A1, uart1_rx_interrupt)
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}
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}
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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}
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#endif /* !RX_WITH_DMA */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@ -107,7 +107,6 @@
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#define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x800
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#define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x800
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#endif /* ELFLOADER_CONF_TEXTMEMORY_SIZE */
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#endif /* ELFLOADER_CONF_TEXTMEMORY_SIZE */
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#define AODV_COMPLIANCE
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#define AODV_COMPLIANCE
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#define AODV_NUM_RT_ENTRIES 32
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#define AODV_NUM_RT_ENTRIES 32
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@ -117,6 +116,8 @@
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#define PROCESS_CONF_STATS 1
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#define PROCESS_CONF_STATS 1
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/*#define PROCESS_CONF_FASTPOLL 4*/
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/*#define PROCESS_CONF_FASTPOLL 4*/
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#define UART1_CONF_RX_WITH_DMA 0
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#ifdef NETSTACK_CONF_WITH_IPV6
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#ifdef NETSTACK_CONF_WITH_IPV6
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#define LINKADDR_CONF_SIZE 8
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#define LINKADDR_CONF_SIZE 8
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@ -134,7 +135,7 @@
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#define UIP_CONF_MAX_ROUTES 30
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#define UIP_CONF_MAX_ROUTES 30
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#endif /* UIP_CONF_MAX_ROUTES */
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#endif /* UIP_CONF_MAX_ROUTES */
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#define UIP_CONF_ND6_SEND_RA 0
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#define UIP_CONF_ND6_SEND_RA 0
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#define UIP_CONF_ND6_REACHABLE_TIME 600000
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#define UIP_CONF_ND6_REACHABLE_TIME 600000
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#define UIP_CONF_ND6_RETRANS_TIMER 10000
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#define UIP_CONF_ND6_RETRANS_TIMER 10000
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@ -147,7 +148,7 @@
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#define UIP_CONF_NETIF_MAX_ADDRESSES 3
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#define UIP_CONF_NETIF_MAX_ADDRESSES 3
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#define UIP_CONF_IP_FORWARD 0
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#define UIP_CONF_IP_FORWARD 0
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#ifndef UIP_CONF_BUFFER_SIZE
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#ifndef UIP_CONF_BUFFER_SIZE
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#define UIP_CONF_BUFFER_SIZE 240
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#define UIP_CONF_BUFFER_SIZE 240
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#endif
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#endif
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#define SICSLOWPAN_CONF_COMPRESSION SICSLOWPAN_COMPRESSION_HC06
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#define SICSLOWPAN_CONF_COMPRESSION SICSLOWPAN_COMPRESSION_HC06
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@ -187,8 +188,6 @@
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#define UIP_CONF_TCP_SPLIT 0
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#define UIP_CONF_TCP_SPLIT 0
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/* include the project config */
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/* include the project config */
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/* PROJECT_CONF_H might be defined in the project Makefile */
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/* PROJECT_CONF_H might be defined in the project Makefile */
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#ifdef PROJECT_CONF_H
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#ifdef PROJECT_CONF_H
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