deac/osd-contiki
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

Merge branch 'master' of git://git.devl.org/git/malvira/mc1322x-tests

Browse source
This commit is contained in:
Mariano Alvira 2009-06-16 18:34:19 -04:00
parent 232faa94d2 c419d7403b
commit 6a1f33a40a
5 changed files with 124 additions and 47 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
include/crm.h
View file

@ -16,7 +16,7 @@
#define CRM_RTC_TIMEOUT (CRM_BASE+0x2c) #define CRM_RTC_TIMEOUT (CRM_BASE+0x2c)
#define CRM_CAL_CNTL (CRM_BASE+0x34) #define CRM_CAL_CNTL (CRM_BASE+0x34)
#define CRM_CAL_COUNT (CRM_BASE+0x38) #define CRM_CAL_COUNT (CRM_BASE+0x38)
#define CRM_RINGOSC_CTNL (CRM_BASE+0x3c) #define CRM_RINGOSC_CNTL (CRM_BASE+0x3c)
#define CRM_XTAL_CNTL (CRM_BASE+0x40) #define CRM_XTAL_CNTL (CRM_BASE+0x40)
#define CRM_XTAL32_CNTL (CRM_BASE+0x44) #define CRM_XTAL32_CNTL (CRM_BASE+0x44)
#define CRM_VREG_CNTL (CRM_BASE+0x48) #define CRM_VREG_CNTL (CRM_BASE+0x48)

5
include/utils.h
View file

@ -4,4 +4,9 @@
#define reg32(x) (*(volatile uint32_t *)(x)) #define reg32(x) (*(volatile uint32_t *)(x))
#define reg16(x) (*(volatile uint16_t *)(x)) #define reg16(x) (*(volatile uint16_t *)(x))
#define bit(bit) (1<<bit)
#define bit_is_set(val,bit) (((val & (1<<bit)) >> bit) == 1)
#define clear_bit(val,bit) (val=(val & ~(1<<bit)))
#define set_bit(val,bit) (val=(val | (1<<bit)))
#endif #endif

71
src/maca.c
View file

@ -160,6 +160,43 @@ void radio_on(void) {
init_phy(); init_phy();
} }
/* initialized with 0x4c */
uint8_t ctov[16] = {
0x0b,
0x0b,
0x0b,
0x0a,
0x0d,
0x0d,
0x0c,
0x0c,
0x0f,
0x0e,
0x0e,
0x0e,
0x11,
0x10,
0x10,
0x0f,
};
/* get_ctov thanks to Umberto */
#define _INIT_CTOV_WORD_1 0x00dfbe77
#define _INIT_CTOV_WORD_2 0x023126e9
uint8_t get_ctov( uint32_t r0, uint32_t r1 )
{
r0 = r0 * _INIT_CTOV_WORD_1;
r0 += ( r1 << 22 );
r0 += _INIT_CTOV_WORD_2;
r0 = (uint32_t)(((int32_t)r0) >> 25);
return (uint8_t)r0;
}
/* radio_init has been tested to be good */ /* radio_init has been tested to be good */
void radio_init(void) { void radio_init(void) {
volatile uint32_t i; volatile uint32_t i;
@ -217,6 +254,19 @@ void radio_init(void) {
puts("\n\r"); puts("\n\r");
} }
puts("radio_init: ctov parameter 0x");
put_hex(ram_values[3]);
puts("\n\r");
for(i=0; i<16; i++) {
ctov[i] = get_ctov(i,ram_values[3]);
puts("radio_init: ctov[");
put_hex(i);
puts("] = 0x");
put_hex(ctov[i]);
puts("\n\r");
}
} }
const uint32_t PSMVAL[19] = { const uint32_t PSMVAL[19] = {
@ -333,25 +383,6 @@ const uint32_t VCODivF[16] = {
0x01555555, 0x01555555,
}; };
const uint8_t ctov_4c[16] = {
0x0b,
0x0b,
0x0b,
0x0a,
0x0d,
0x0d,
0x0c,
0x0c,
0x0f,
0x0e,
0x0e,
0x0e,
0x11,
0x10,
0x10,
0x0f,
};
/* tested good */ /* tested good */
#define ADDR_CHAN1 0x80009800 #define ADDR_CHAN1 0x80009800
#define ADDR_CHAN2 (ADDR_CHAN1+12) #define ADDR_CHAN2 (ADDR_CHAN1+12)
@ -376,7 +407,7 @@ void set_channel(uint8_t chan) {
reg(ADDR_CHAN4) = tmp; reg(ADDR_CHAN4) = tmp;
tmp = tmp & 0xffffe0ff; tmp = tmp & 0xffffe0ff;
tmp = tmp | (((ctov_4c[chan])<<8)&0x1F00); tmp = tmp | (((ctov[chan])<<8)&0x1F00);
reg(ADDR_CHAN4) = tmp; reg(ADDR_CHAN4) = tmp;
/* duh! */ /* duh! */
} }

8
tests/rftest-tx.c
View file

@ -1,4 +1,5 @@
#define GPIO_FUNC_SEL0 0x80000018 /* GPIO 15 - 0; 2 bit blocks */ #define GPIO_FUNC_SEL0 0x80000018 /* GPIO 15 - 0; 2 bit blocks */
#define GPIO_FUNC_SEL2 0x80000020 /* GPIO 47 - 32; 2 bit blocks */
#define BASE_UART1 0x80005000 #define BASE_UART1 0x80005000
#define UART1_CON 0x80005000 #define UART1_CON 0x80005000
@ -18,7 +19,7 @@
#define reg(x) (*(volatile uint32_t *)(x)) #define reg(x) (*(volatile uint32_t *)(x))
#define DELAY 200000 #define DELAY 100000
#define DATA 0x00401000; #define DATA 0x00401000;
#define NL "\033[K\r\n" #define NL "\033[K\r\n"
@ -59,7 +60,7 @@ uint32_t ackBox[10];
maca_control = (control_prm | control_asap | control_seq_rx); \ maca_control = (control_prm | control_asap | control_seq_rx); \
}while(FALSE) }while(FALSE)
#define PAYLOAD_LEN 96 /* not including the extra 4 bytes for len+fcs+somethingelse */ #define PAYLOAD_LEN 16 /* not including the extra 4 bytes for len+fcs+somethingelse */
/* maca dmatx needs extra 4 bytes for checksum */ /* maca dmatx needs extra 4 bytes for checksum */
/* needs + 4 bytes for len(1 byte) + fcs(2 bytes) + somethingelse */ /* needs + 4 bytes for len(1 byte) + fcs(2 bytes) + somethingelse */
#define command_xcvr_tx() \ #define command_xcvr_tx() \
@ -168,6 +169,9 @@ void main(void) {
/* puts("reserved modem_base\n\r"); */ /* puts("reserved modem_base\n\r"); */
/* dump_regs(0x80009200, 192); */ /* dump_regs(0x80009200, 192); */
reg(GPIO_FUNC_SEL2) = (0x01 << ((44-16*2)*2));
reg(GPIO_PAD_DIR0) = reg(GPIO_PAD_DIR0) | (1<<(44-32));
fill_data(); fill_data();
command_xcvr_tx(); command_xcvr_tx();

85
tests/sleep.c
View file

@ -7,12 +7,6 @@
#define GPIO_PAD_PU_EN1 0x80000014 #define GPIO_PAD_PU_EN1 0x80000014
#define ADC_CONTROL 0x80000018 #define ADC_CONTROL 0x80000018
#define CRM_WU_CNTL 0x80003004
#define CRM_WU_TIMEOUT 0x80003024
#define CRM_SLEEP_CNTL 0x80003008
#define CRM_STATUS 0x80003018
#define CRM_XTAL_CNTL 0x80000040
#define BASE_UART1 0x80005000 #define BASE_UART1 0x80005000
#define UART1_CON 0x80005000 #define UART1_CON 0x80005000
#define UART1_STAT 0x80005004 #define UART1_STAT 0x80005004
@ -24,10 +18,13 @@
#define DELAY 400000 #define DELAY 400000
#define USE_32KHZ 1
#include "embedded_types.h" #include "embedded_types.h"
#include "isr.h" #include "isr.h"
#include "utils.h" #include "utils.h"
#include "maca.h" #include "maca.h"
#include "crm.h"
void putc(uint8_t c); void putc(uint8_t c);
void puts(uint8_t *s); void puts(uint8_t *s);
@ -59,27 +56,27 @@ void (*crm_gotosleep)(crmSleepCtrl_t *foo) = 0x0000364d;
__attribute__ ((section ("startup"))) void main(void) { __attribute__ ((section ("startup"))) void main(void) {
crmSleepCtrl_t crmSleepCtrl; crmSleepCtrl_t crmSleepCtrl;
reg32(GPIO_PAD_DIR0) = 0x00000100; // reg32(GPIO_PAD_DIR0) = 0x00000100;
reg32(GPIO_DATA0) = 0x00000100; // reg32(GPIO_DATA0) = 0x00000100;
/* Restore UART regs. to default */ /* Restore UART regs. to default */
/* in case there is still bootloader state leftover */ /* in case there is still bootloader state leftover */
*(volatile uint32_t *)UART1_CON = 0x0000c800; /* mask interrupts, 16 bit sample --- helps explain the baud rate */ // *(volatile uint32_t *)UART1_CON = 0x0000c800; /* mask interrupts, 16 bit sample --- helps explain the baud rate */
/* INC = 767; MOD = 9999 works: 115200 @ 24 MHz 16 bit sample */ /* INC = 767; MOD = 9999 works: 115200 @ 24 MHz 16 bit sample */
#define INC 767 #define INC 767
#define MOD 9999 #define MOD 9999
*(volatile uint32_t *)UART1_BR = INC<<16 | MOD; // *(volatile uint32_t *)UART1_BR = INC<<16 | MOD;
/* see Section 11.5.1.2 Alternate Modes */ /* see Section 11.5.1.2 Alternate Modes */
/* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */ /* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */
/* From the datasheet: "The peripheral function will control operation of the pad IF */ /* From the datasheet: "The peripheral function will control operation of the pad IF */
/* THE PERIPHERAL IS ENABLED. */ /* THE PERIPHERAL IS ENABLED. */
*(volatile uint32_t *)UART1_CON = 0x00000003; /* enable receive and transmit */ // *(volatile uint32_t *)UART1_CON = 0x00000003; /* enable receive and transmit */
*(volatile uint32_t *)GPIO_FUNC_SEL0 = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/ // *(volatile uint32_t *)GPIO_FUNC_SEL0 = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/
reg32(0x00401ffc) = 0x01234567; reg32(0x00401ffc) = 0x01234567;
reg32(0x00407ffc) = 0xdeadbeef; reg32(0x00407ffc) = 0xdeadbeef;
@ -107,31 +104,71 @@ __attribute__ ((section ("startup"))) void main(void) {
/* disable all pullups */ /* disable all pullups */
/* seems to make a slight difference (2.0uA vs 1.95uA)*/ /* seems to make a slight difference (2.0uA vs 1.95uA)*/
// reg32(GPIO_PAD_PU_EN0) = 0; reg32(GPIO_PAD_PU_EN0) = 0;
// reg32(GPIO_PAD_PU_EN1) = 0; reg32(GPIO_PAD_PU_EN1) = 0;
// reg16(ADC_CONTROL) = 0; /* internal Vref2 */ reg16(ADC_CONTROL) = 0; /* internal Vref2 */
reg16(CRM_XTAL_CNTL) = 0x052; /* default is 0xf52 */ /* doesn't anything w.r.t. power */
#if USE_32KHZ
/* turn on the 32kHz crystal */
puts("enabling 32kHz crystal\n\r");
/* you have to hold it's hand with this on */
/* once you start the 32xHz crystal it can only be stopped with a reset (hard or soft) */
/* first, disable the ring osc */
clear_bit(reg32(CRM_RINGOSC_CNTL),0);
/* enable the 32kHZ crystal */
set_bit(reg32(CRM_XTAL32_CNTL),0);
/* set the XTAL32_EXISTS bit */
/* the datasheet says to do this after you've check that RTC_COUNT is changing */
/* the datasheet is not correct */
set_bit(reg32(CRM_SYS_CNTL),5);
{
static volatile uint32_t old;
old = reg32(CRM_RTC_COUNT);
puts("waiting for xtal\n\r");
while(reg32(CRM_RTC_COUNT) == old) {
continue;
}
/* RTC has started up */
set_bit(reg32(CRM_SYS_CNTL),5);
puts("32kHZ xtal started\n\r");
}
#endif
// reg16(CRM_XTAL_CNTL) = 0x052; /* default is 0xf52 */ /* doesn't anything w.r.t. power */
/* go to sleep */ /* go to sleep */
// reg32(CRM_WU_CNTL) = 0; /* don't wake up */ // reg32(CRM_WU_CNTL) = 0; /* don't wake up */
reg32(CRM_WU_CNTL) = 0x1; /* enable wakeup from wakeup timer */ reg32(CRM_WU_CNTL) = 0x1; /* enable wakeup from wakeup timer */
// reg32(CRM_WU_TIMEOUT) = 1875000; /* wake 10 sec later if doze */ // reg32(CRM_WU_TIMEOUT) = 1875000; /* wake 10 sec later if doze */
reg32(CRM_WU_TIMEOUT) = 20000; /* wake 10 sec later if hibernate w/2kHz*/ #if USE_32KHZ
reg32(CRM_WU_TIMEOUT) = 327680*2;
#else
reg32(CRM_WU_TIMEOUT) = 20000; /* wake 10 sec later if hibernate w/2kHz*/
#endif
// reg32(CRM_SLEEP_CNTL) = 1; /* hibernate, RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 2.0uA */ /* hobby board: 2kHz = 11uA; 32kHz = 11uA */
// reg32(CRM_SLEEP_CNTL) = 0x41; /* hibernate, RAM page 0 only, retain state, don't power GPIO */ /* approx. 10.0uA */ // reg32(CRM_SLEEP_CNTL) = 1; /* hibernate, RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 2kHz = 2.0uA */
// reg32(CRM_SLEEP_CNTL) = 0x51; /* hibernate, RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 11.7uA */ /* hobby board: 2kHz = 18uA; 32kHz = 19uA */
// reg32(CRM_SLEEP_CNTL) = 0x61; /* hibernate, RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 13.9uA */ // reg32(CRM_SLEEP_CNTL) = 0x41; /* hibernate, RAM page 0 only, retain state, don't power GPIO */ /* approx. 2kHz = 10.0uA */
// reg32(CRM_SLEEP_CNTL) = 0x71; /* hibernate, all RAM pages, retain state, don't power GPIO */ /* approx. 16.1uA - possibly with periodic refresh*/ /* hobby board: 2kHz = 20uA; 32kHz = 21uA */
reg32(CRM_SLEEP_CNTL) = 0xf1; /* hibernate, all RAM pages, retain state, power GPIO */ /* approx. 16.1uA - possibly with periodic refresh*/ // reg32(CRM_SLEEP_CNTL) = 0x51; /* hibernate, RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 2kHz = 11.7uA */
/* hobby board: 2kHz = 22uA; 32kHz = 22.5uA */
// reg32(CRM_SLEEP_CNTL) = 0x61; /* hibernate, RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 2kHz = 13.9uA */
/* hobby board: 2kHz = 24uA; 32kHz = 25uA */
// reg32(CRM_SLEEP_CNTL) = 0x71; /* hibernate, all RAM pages, retain state, don't power GPIO */ /* approx. 2kHz = 16.1uA */
// reg32(CRM_SLEEP_CNTL) = 0xf1; /* hibernate, all RAM pages, retain state, power GPIO */ /* consumption depends on GPIO hookup */
// reg32(CRM_SLEEP_CNTL) = 2; /* doze , RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 69.2 uA */ // reg32(CRM_SLEEP_CNTL) = 2; /* doze , RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 69.2 uA */
// reg32(CRM_SLEEP_CNTL) = 0x42; /* doze , RAM page 0 only, retain state, don't power GPIO */ /* approx. 77.3uA */ // reg32(CRM_SLEEP_CNTL) = 0x42; /* doze , RAM page 0 only, retain state, don't power GPIO */ /* approx. 77.3uA */
// reg32(CRM_SLEEP_CNTL) = 0x52; /* doze , RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 78.9uA */ // reg32(CRM_SLEEP_CNTL) = 0x52; /* doze , RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 78.9uA */
// reg32(CRM_SLEEP_CNTL) = 0x62; /* doze , RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 81.2uA */ // reg32(CRM_SLEEP_CNTL) = 0x62; /* doze , RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 81.2uA */
// reg32(CRM_SLEEP_CNTL) = 0x72; /* doze , all RAM pages, retain state, don't power GPIO */ /* approx. 83.4uA - possibly with periodic refresh*/ // reg32(CRM_SLEEP_CNTL) = 0x72; /* doze , all RAM pages, retain state, don't power GPIO */ /* approx. 83.4uA - possibly with periodic refresh*/
// reg32(CRM_SLEEP_CNTL) = 0xf2; /* doze , all RAM pages, retain state, power GPIO */ /* approx. 82.8uA - possibly with periodic refresh*/ // reg32(CRM_SLEEP_CNTL) = 0xf2; /* doze , all RAM pages, retain state, power GPIO */ /* consumption depends on GPIO hookup */
/* crmSleepCtrl.sleepType = 0; */ /* crmSleepCtrl.sleepType = 0; */