Merge branch 'master' of git://git.devl.org/git/malvira/mc1322x-tests
This commit is contained in:
Mariano Alvira
commit
6a1f33a40a
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@ -16,7 +16,7 @@
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#define CRM_RTC_TIMEOUT (CRM_BASE+0x2c)
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#define CRM_CAL_CNTL (CRM_BASE+0x34)
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#define CRM_CAL_COUNT (CRM_BASE+0x38)
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#define CRM_RINGOSC_CTNL (CRM_BASE+0x3c)
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#define CRM_RINGOSC_CNTL (CRM_BASE+0x3c)
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#define CRM_XTAL_CNTL (CRM_BASE+0x40)
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#define CRM_XTAL32_CNTL (CRM_BASE+0x44)
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#define CRM_VREG_CNTL (CRM_BASE+0x48)
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@ -4,4 +4,9 @@
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#define reg32(x) (*(volatile uint32_t *)(x))
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#define reg16(x) (*(volatile uint16_t *)(x))
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#define bit(bit) (1<<bit)
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#define bit_is_set(val,bit) (((val & (1<<bit)) >> bit) == 1)
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#define clear_bit(val,bit) (val=(val & ~(1<<bit)))
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#define set_bit(val,bit) (val=(val | (1<<bit)))
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#endif
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71
src/maca.c
71
src/maca.c
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@ -160,6 +160,43 @@ void radio_on(void) {
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init_phy();
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}
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/* initialized with 0x4c */
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uint8_t ctov[16] = {
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0x0b,
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0x0b,
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0x0b,
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0x0a,
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0x0d,
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0x0d,
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0x0c,
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0x0c,
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0x0f,
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0x0e,
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0x0e,
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0x0e,
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0x11,
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0x10,
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0x10,
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0x0f,
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};
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/* get_ctov thanks to Umberto */
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#define _INIT_CTOV_WORD_1 0x00dfbe77
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#define _INIT_CTOV_WORD_2 0x023126e9
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uint8_t get_ctov( uint32_t r0, uint32_t r1 )
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{
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r0 = r0 * _INIT_CTOV_WORD_1;
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r0 += ( r1 << 22 );
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r0 += _INIT_CTOV_WORD_2;
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r0 = (uint32_t)(((int32_t)r0) >> 25);
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return (uint8_t)r0;
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}
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/* radio_init has been tested to be good */
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void radio_init(void) {
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volatile uint32_t i;
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@ -217,6 +254,19 @@ void radio_init(void) {
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puts("\n\r");
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}
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puts("radio_init: ctov parameter 0x");
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put_hex(ram_values[3]);
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puts("\n\r");
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for(i=0; i<16; i++) {
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ctov[i] = get_ctov(i,ram_values[3]);
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puts("radio_init: ctov[");
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put_hex(i);
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puts("] = 0x");
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put_hex(ctov[i]);
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puts("\n\r");
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}
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}
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const uint32_t PSMVAL[19] = {
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@ -333,25 +383,6 @@ const uint32_t VCODivF[16] = {
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0x01555555,
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};
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const uint8_t ctov_4c[16] = {
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0x0b,
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0x0b,
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0x0b,
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0x0a,
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0x0d,
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0x0d,
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0x0c,
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0x0c,
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0x0f,
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0x0e,
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0x0e,
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0x0e,
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0x11,
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0x10,
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0x10,
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0x0f,
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};
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/* tested good */
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#define ADDR_CHAN1 0x80009800
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#define ADDR_CHAN2 (ADDR_CHAN1+12)
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@ -376,7 +407,7 @@ void set_channel(uint8_t chan) {
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reg(ADDR_CHAN4) = tmp;
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tmp = tmp & 0xffffe0ff;
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tmp = tmp | (((ctov_4c[chan])<<8)&0x1F00);
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tmp = tmp | (((ctov[chan])<<8)&0x1F00);
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reg(ADDR_CHAN4) = tmp;
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/* duh! */
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}
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@ -1,4 +1,5 @@
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#define GPIO_FUNC_SEL0 0x80000018 /* GPIO 15 - 0; 2 bit blocks */
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#define GPIO_FUNC_SEL2 0x80000020 /* GPIO 47 - 32; 2 bit blocks */
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#define BASE_UART1 0x80005000
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#define UART1_CON 0x80005000
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@ -18,7 +19,7 @@
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#define reg(x) (*(volatile uint32_t *)(x))
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#define DELAY 200000
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#define DELAY 100000
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#define DATA 0x00401000;
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#define NL "\033[K\r\n"
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@ -59,7 +60,7 @@ uint32_t ackBox[10];
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maca_control = (control_prm | control_asap | control_seq_rx); \
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}while(FALSE)
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#define PAYLOAD_LEN 96 /* not including the extra 4 bytes for len+fcs+somethingelse */
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#define PAYLOAD_LEN 16 /* not including the extra 4 bytes for len+fcs+somethingelse */
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/* maca dmatx needs extra 4 bytes for checksum */
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/* needs + 4 bytes for len(1 byte) + fcs(2 bytes) + somethingelse */
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#define command_xcvr_tx() \
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@ -168,6 +169,9 @@ void main(void) {
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/* puts("reserved modem_base\n\r"); */
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/* dump_regs(0x80009200, 192); */
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reg(GPIO_FUNC_SEL2) = (0x01 << ((44-16*2)*2));
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reg(GPIO_PAD_DIR0) = reg(GPIO_PAD_DIR0) | (1<<(44-32));
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fill_data();
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command_xcvr_tx();
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@ -7,12 +7,6 @@
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#define GPIO_PAD_PU_EN1 0x80000014
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#define ADC_CONTROL 0x80000018
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#define CRM_WU_CNTL 0x80003004
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#define CRM_WU_TIMEOUT 0x80003024
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#define CRM_SLEEP_CNTL 0x80003008
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#define CRM_STATUS 0x80003018
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#define CRM_XTAL_CNTL 0x80000040
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#define BASE_UART1 0x80005000
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#define UART1_CON 0x80005000
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#define UART1_STAT 0x80005004
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@ -24,10 +18,13 @@
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#define DELAY 400000
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#define USE_32KHZ 1
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#include "embedded_types.h"
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#include "isr.h"
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#include "utils.h"
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#include "maca.h"
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#include "crm.h"
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void putc(uint8_t c);
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void puts(uint8_t *s);
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@ -59,27 +56,27 @@ void (*crm_gotosleep)(crmSleepCtrl_t *foo) = 0x0000364d;
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__attribute__ ((section ("startup"))) void main(void) {
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crmSleepCtrl_t crmSleepCtrl;
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reg32(GPIO_PAD_DIR0) = 0x00000100;
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// reg32(GPIO_PAD_DIR0) = 0x00000100;
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reg32(GPIO_DATA0) = 0x00000100;
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// reg32(GPIO_DATA0) = 0x00000100;
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/* Restore UART regs. to default */
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/* in case there is still bootloader state leftover */
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*(volatile uint32_t *)UART1_CON = 0x0000c800; /* mask interrupts, 16 bit sample --- helps explain the baud rate */
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// *(volatile uint32_t *)UART1_CON = 0x0000c800; /* mask interrupts, 16 bit sample --- helps explain the baud rate */
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/* INC = 767; MOD = 9999 works: 115200 @ 24 MHz 16 bit sample */
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#define INC 767
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#define MOD 9999
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*(volatile uint32_t *)UART1_BR = INC<<16 | MOD;
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// *(volatile uint32_t *)UART1_BR = INC<<16 | MOD;
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/* see Section 11.5.1.2 Alternate Modes */
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/* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */
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/* From the datasheet: "The peripheral function will control operation of the pad IF */
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/* THE PERIPHERAL IS ENABLED. */
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*(volatile uint32_t *)UART1_CON = 0x00000003; /* enable receive and transmit */
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*(volatile uint32_t *)GPIO_FUNC_SEL0 = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/
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// *(volatile uint32_t *)UART1_CON = 0x00000003; /* enable receive and transmit */
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// *(volatile uint32_t *)GPIO_FUNC_SEL0 = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/
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reg32(0x00401ffc) = 0x01234567;
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reg32(0x00407ffc) = 0xdeadbeef;
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@ -107,31 +104,71 @@ __attribute__ ((section ("startup"))) void main(void) {
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/* disable all pullups */
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/* seems to make a slight difference (2.0uA vs 1.95uA)*/
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// reg32(GPIO_PAD_PU_EN0) = 0;
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// reg32(GPIO_PAD_PU_EN1) = 0;
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// reg16(ADC_CONTROL) = 0; /* internal Vref2 */
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reg32(GPIO_PAD_PU_EN0) = 0;
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reg32(GPIO_PAD_PU_EN1) = 0;
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reg16(ADC_CONTROL) = 0; /* internal Vref2 */
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// reg16(CRM_XTAL_CNTL) = 0x052; /* default is 0xf52 */ /* doesn't anything w.r.t. power */
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reg16(CRM_XTAL_CNTL) = 0x052; /* default is 0xf52 */ /* doesn't anything w.r.t. power */
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#if USE_32KHZ
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/* turn on the 32kHz crystal */
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puts("enabling 32kHz crystal\n\r");
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/* you have to hold it's hand with this on */
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/* once you start the 32xHz crystal it can only be stopped with a reset (hard or soft) */
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/* first, disable the ring osc */
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clear_bit(reg32(CRM_RINGOSC_CNTL),0);
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/* enable the 32kHZ crystal */
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set_bit(reg32(CRM_XTAL32_CNTL),0);
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/* set the XTAL32_EXISTS bit */
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/* the datasheet says to do this after you've check that RTC_COUNT is changing */
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/* the datasheet is not correct */
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set_bit(reg32(CRM_SYS_CNTL),5);
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{
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static volatile uint32_t old;
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old = reg32(CRM_RTC_COUNT);
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puts("waiting for xtal\n\r");
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while(reg32(CRM_RTC_COUNT) == old) {
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continue;
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}
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/* RTC has started up */
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set_bit(reg32(CRM_SYS_CNTL),5);
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puts("32kHZ xtal started\n\r");
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}
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#endif
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/* go to sleep */
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// reg32(CRM_WU_CNTL) = 0; /* don't wake up */
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reg32(CRM_WU_CNTL) = 0x1; /* enable wakeup from wakeup timer */
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// reg32(CRM_WU_TIMEOUT) = 1875000; /* wake 10 sec later if doze */
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reg32(CRM_WU_TIMEOUT) = 20000; /* wake 10 sec later if hibernate w/2kHz*/
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#if USE_32KHZ
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reg32(CRM_WU_TIMEOUT) = 327680*2;
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#else
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reg32(CRM_WU_TIMEOUT) = 20000; /* wake 10 sec later if hibernate w/2kHz*/
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#endif
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// reg32(CRM_SLEEP_CNTL) = 1; /* hibernate, RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 2.0uA */
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// reg32(CRM_SLEEP_CNTL) = 0x41; /* hibernate, RAM page 0 only, retain state, don't power GPIO */ /* approx. 10.0uA */
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// reg32(CRM_SLEEP_CNTL) = 0x51; /* hibernate, RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 11.7uA */
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// reg32(CRM_SLEEP_CNTL) = 0x61; /* hibernate, RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 13.9uA */
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// reg32(CRM_SLEEP_CNTL) = 0x71; /* hibernate, all RAM pages, retain state, don't power GPIO */ /* approx. 16.1uA - possibly with periodic refresh*/
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reg32(CRM_SLEEP_CNTL) = 0xf1; /* hibernate, all RAM pages, retain state, power GPIO */ /* approx. 16.1uA - possibly with periodic refresh*/
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/* hobby board: 2kHz = 11uA; 32kHz = 11uA */
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// reg32(CRM_SLEEP_CNTL) = 1; /* hibernate, RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 2kHz = 2.0uA */
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/* hobby board: 2kHz = 18uA; 32kHz = 19uA */
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// reg32(CRM_SLEEP_CNTL) = 0x41; /* hibernate, RAM page 0 only, retain state, don't power GPIO */ /* approx. 2kHz = 10.0uA */
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/* hobby board: 2kHz = 20uA; 32kHz = 21uA */
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// reg32(CRM_SLEEP_CNTL) = 0x51; /* hibernate, RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 2kHz = 11.7uA */
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/* hobby board: 2kHz = 22uA; 32kHz = 22.5uA */
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// reg32(CRM_SLEEP_CNTL) = 0x61; /* hibernate, RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 2kHz = 13.9uA */
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/* hobby board: 2kHz = 24uA; 32kHz = 25uA */
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// reg32(CRM_SLEEP_CNTL) = 0x71; /* hibernate, all RAM pages, retain state, don't power GPIO */ /* approx. 2kHz = 16.1uA */
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// reg32(CRM_SLEEP_CNTL) = 0xf1; /* hibernate, all RAM pages, retain state, power GPIO */ /* consumption depends on GPIO hookup */
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// reg32(CRM_SLEEP_CNTL) = 2; /* doze , RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 69.2 uA */
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// reg32(CRM_SLEEP_CNTL) = 0x42; /* doze , RAM page 0 only, retain state, don't power GPIO */ /* approx. 77.3uA */
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// reg32(CRM_SLEEP_CNTL) = 0x52; /* doze , RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 78.9uA */
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// reg32(CRM_SLEEP_CNTL) = 0x62; /* doze , RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 81.2uA */
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// reg32(CRM_SLEEP_CNTL) = 0x72; /* doze , all RAM pages, retain state, don't power GPIO */ /* approx. 83.4uA - possibly with periodic refresh*/
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// reg32(CRM_SLEEP_CNTL) = 0xf2; /* doze , all RAM pages, retain state, power GPIO */ /* approx. 82.8uA - possibly with periodic refresh*/
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// reg32(CRM_SLEEP_CNTL) = 0xf2; /* doze , all RAM pages, retain state, power GPIO */ /* consumption depends on GPIO hookup */
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/* crmSleepCtrl.sleepType = 0; */
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